Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-03
2001-06-12
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S290000, C438S291000, C438S282000, C438S526000, C257S368000
Reexamination Certificate
active
06245618
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor device comprising transistors, and to a method of manufacturing the semiconductor device. The present invention has particular applicability in manufacturing a reliable high-density Metal Oxide Semiconductor Field Effect transistor (MOSFET) device with submicron dimensions.
BACKGROUND ART
The escalating requirements for high performance and density associated with ultra large scale integration semiconductor devices require high speed and reliability and increased manufacturing throughput for competitiveness. As gate lengths are reduced to increase the speed and density, problems such as short channel effects are encountered. For example. “punch through” arises when the drain voltage reaches a sufficient large value, and the depletion layer associated with the drain spreads across the substrate and reaches the source, thereby enabling the charge carriers in the drain region to punch through to the source. In addition, “hot carrier injection” arises when device dimensions are reduced but the supply voltage is maintained, thereby increasing the electric field generated in the silicon substrate. Such an increased electric field enables electrons in the channel region to gain sufficient energy to be injected onto the gate oxide, resulting in device degradation.
Various methods have been proposed to solve the short channel effects. According to the method disclosed in U.S. Pat. No. 5,602,045 by Kimura, shallow source/drain regions are formed within amorphous regions to suppress an increase of dislocated charge carriers at the interface between the amorphous region and substrate. As shown in
FIG. 1
, pocket regions
18
are formed in the surface portions of a p-well region
12
formed in the surface portion of a semiconductor substrate
10
, by ion implanting a p type impurity, as shown by arrows A, employing gate oxide
16
, gate electrode
17
and field oxide regions
14
as a mask. Then, lightly doped impurity layers
20
are formed within the confines of the pocket regions
18
by ion implanting an n type impurity, as shown by arrows B in FIG.
2
.
After forming SiO
2
sidewall spacers
30
on the side surfaces of the gate electrode
17
and gate oxide
16
, as shown in
FIG. 3
, amorphous layers
32
are formed within the confines of the lightly doped impurity layers
20
, by implanting ions with large mass numbers, e.g., Si, Ge, As, as shown by arrows C, employing the gate oxide
16
, gate electrode
17
, sidewall spacers
30
and field oxide
14
as a mask. The depth of amorphous layers
32
is determined to be greater than the depth of subsequently formed impurity layers
40
. The amorphous layers
32
are formed while cooling the substrate
10
and well region
12
to reduce junction leak current from the impurity layers
40
to the well region
12
.
As shown in
FIG. 4
, the impurity layers
40
are then formed by ion implanting an n type impurity, as shown by arrows D, to a depth smaller than that of the amorphous layer
32
even after a subsequent annealing step, thereby suppressing dislocated carrier charges at the interface between the amorphous layers
32
and the well region
12
. As shown in
FIG. 4
, the resulting device comprises the shallow impurity layers
40
formed within the confines of the amorphous regions
32
which, in turn, are within the confines of the light doped impurity layers
20
. Accordingly, the method disclosed in U.S. Pat. No. 5,602,045 forms the shallow impurity regions
40
, obtaining reduced junction leakage. However, the amorphous layers
32
. formed between the impurity regions
40
and lightly doped impurity layers
20
, reduce the mobility of the carriers moving between the impurity regions
40
and lightly doped impurity layers
20
, thereby reducing the device speed.
There is a need for efficient methodology for manufacturing a semiconductor device exhibiting improved short channel characteristics.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is a simplified, efficient and production worthy methodology for manufacturing a MOSFET exhibiting improved short channel characteristics.
Another advantage of the present invention is a semiconductor device exhibiting improved short channel characteristics.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following description or may be learned from the practice of the present invention. The objectives and advantages of the present invention maybe realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing semiconductor device, the method comprising: forming a first conductivity type impurity source/drain regions with a channel region therebetween in a portion of a main surface of a substrate containing a second conductivity type; ion implanting atoms into the substrate to form a buried amorphous region below the channel region; and ion implanting a second conductivity type impurity into the substrate to form a retrograde impurity region having an impurity concentration peak within the confines of the buried amorphous region.
Another aspect of the present invention is a semiconductor comprising: a substrate containing a first conductivity type impurity; source/drain regions formed in the substrate with a channel region therebetween; a gate dielectric layer overlying the channel region; a gate electrode on the gate dielectric layer; a buried amorphous region formed below the channel region; and a retrograde impurity region, formed in the substrate, comprising an impurity concentration peak within the confines of the buried amorphous region.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustrating the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive.
REFERENCES:
patent: 4633289 (1986-12-01), Chen
patent: 5602045 (1997-02-01), Kimura
patent: 5675176 (1997-10-01), Ushiku et al.
John Yuan-Tai Chen, “Quadruple-Well CMOS for VLSI Technology”, IEEE Transactions on Electron Devices, vol. ED-31, No. 7, Jul. 1984.
An Judy X.
Yu Bin
Advanced Micro Devices , Inc.
Pham Long
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