MOSFET power transistors and methods

Details MOSFET power transistors and methods MOSFET power transistors and methods

2005-10-25

2005-10-25

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S156000, C438S242000, C438S246000, C438S268000, C438S386000, C438S589000, C438S648000, C438S702000, C438S243000, C438S244000

Reexamination Certificate

active

06958275

ABSTRACT:
Trench MOSFETs and self aligned processes for fabricating trench MOSFETs. These processes produce a higher density of trenches per unit area than can be obtained using prior art masking techniques. The invention self aligns all processing steps (implants, etches, depositions, etc.) to a single mask, thus reducing the pitch of the trenches by the added distances required for multiple masking photolithographic tolerances. The invention also places the source regions and contacts within the side walls of the trenches, thus eliminating the lateral dimensions required, for masking and source depositions or implants from the top surface, from the pitch of the trenches. Various embodiments are disclosed.

REFERENCES:
patent: 2444255 (1948-06-01), Hewlett
patent: 3295030 (1966-12-01), Allison
patent: 3407343 (1968-10-01), Fang
patent: 3427708 (1969-02-01), Hans-Jurgen Schutze et al.
patent: 3458798 (1969-07-01), Fang et al.
patent: 3566215 (1971-02-01), Heywang
patent: 3586925 (1971-06-01), Collard
patent: 3617824 (1971-11-01), Shinoda et al.
patent: 3619737 (1971-11-01), Chiu
patent: 3749987 (1973-07-01), Anantha
patent: 3769109 (1973-10-01), MacRae et al.
patent: 3864819 (1975-02-01), Ying
patent: 3935586 (1976-01-01), Landheer et al.
patent: 3943547 (1976-03-01), Nagano et al.
patent: 3988765 (1976-10-01), Pikor
patent: 4019248 (1977-04-01), Black
patent: 4045250 (1977-08-01), Dingwall
patent: 4099260 (1978-07-01), Lynes et al.
patent: 4104086 (1978-08-01), Bondur et al.
patent: 4138280 (1979-02-01), Rodov
patent: 4139880 (1979-02-01), Ulmer et al.
patent: 4139935 (1979-02-01), Bertin et al.
patent: 4140560 (1979-02-01), Rodov
patent: 4153904 (1979-05-01), Tasch, Jr. et al.
patent: 4246502 (1981-01-01), Kubinec
patent: 4318751 (1982-03-01), Horng
patent: 4330384 (1982-05-01), Okudaira et al.
patent: 4340900 (1982-07-01), Goronkin
patent: 4372034 (1983-02-01), Bohr
patent: 4403396 (1983-09-01), Stein
patent: 4423456 (1983-12-01), Zaidenweber
patent: 4508579 (1985-04-01), Goth et al.
patent: 4533988 (1985-08-01), Daly et al.
patent: 4534826 (1985-08-01), Goth et al.
patent: 4579626 (1986-04-01), Wallace
patent: 4586075 (1986-04-01), Schwenk et al.
patent: 4638551 (1987-01-01), Einthoven
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4672736 (1987-06-01), Westermeier
patent: 4672738 (1987-06-01), Stengl et al.
patent: 4680601 (1987-07-01), Mitlehner et al.
patent: 4739386 (1988-04-01), Tanizawa
patent: 4742377 (1988-05-01), Einthoven
patent: 4745395 (1988-05-01), Robinson
patent: 4757031 (1988-07-01), Kuhnert et al.
patent: 4774560 (1988-09-01), Coe
patent: 4777580 (1988-10-01), Bingham
patent: 4808542 (1989-02-01), Reichert et al.
patent: 4811065 (1989-03-01), Cogan
patent: 4822757 (1989-04-01), Sadamori
patent: 4857985 (1989-08-01), Miller
patent: 4875151 (1989-10-01), Ellsworth et al.
patent: 4900692 (1990-02-01), Robinson
patent: 4903189 (1990-02-01), Ngo et al.
patent: 4927772 (1990-05-01), Arthur et al.
patent: 4974050 (1990-11-01), Fuchs
patent: 5038266 (1991-08-01), Callen et al.
patent: 5047355 (1991-09-01), Huber et al.
patent: 5081509 (1992-01-01), Kozaka et al.
patent: 5093693 (1992-03-01), Abbas et al.
patent: 5101254 (1992-03-01), Hamana
patent: 5109256 (1992-04-01), De Long
patent: 5132749 (1992-07-01), Nishibayashi et al.
patent: 5144547 (1992-09-01), Masamoto
patent: 5168331 (1992-12-01), Yilmaz
patent: 5184198 (1993-02-01), Bartur
patent: 5225376 (1993-07-01), Feaver et al.
patent: 5258640 (1993-11-01), Hsieh et al.
patent: 5268833 (1993-12-01), Axer
patent: 5270239 (1993-12-01), Min et al.
patent: 5296406 (1994-03-01), Readdie et al.
patent: 5298780 (1994-03-01), Harada
patent: 5340757 (1994-08-01), Chantre et al.
patent: 5349224 (1994-09-01), Gilbert et al.
patent: 5349230 (1994-09-01), Shigekane
patent: 5357131 (1994-10-01), Sunami et al.
patent: 5365102 (1994-11-01), Mehrotra et al.
patent: 5396087 (1995-03-01), Baliga
patent: 5426325 (1995-06-01), Chang et al.
patent: 5430323 (1995-07-01), Yamazaki et al.
patent: 5469103 (1995-11-01), Shigekane
patent: 5475245 (1995-12-01), Kudo et al.
patent: 5475252 (1995-12-01), Merrill et al.
patent: 5479626 (1995-12-01), Bindloss et al.
patent: 5506421 (1996-04-01), Palmour
patent: 5510641 (1996-04-01), Yee et al.
patent: 5536676 (1996-07-01), Cheng et al.
patent: 5780324 (1998-07-01), Tokura et al.
patent: 5818084 (1998-10-01), Williams et al.
patent: 5825079 (1998-10-01), Metzler et al.
patent: 5885864 (1999-03-01), Ma
patent: 5886383 (1999-03-01), Kinzer
patent: 5907181 (1999-05-01), Han et al.
patent: 6002574 (1999-12-01), Metzler et al.
patent: 6083846 (2000-07-01), Fulford, Jr. et al.
patent: 6186408 (2001-02-01), Rodov et al.
patent: 6396090 (2002-05-01), Hsu et al.
patent: 6420757 (2002-07-01), Metzler
patent: 6433370 (2002-08-01), Metzler
patent: 6737323 (2004-05-01), Mo
patent: 2003/0003637 (2003-01-01), Ninomiya
patent: 32 19 888 (1983-12-01), None
patent: 196 05 633 (1996-12-01), None
patent: 10231202 (2004-02-01), None
patent: 0 720 235 (1996-07-01), None
patent: 0 795 911 (1997-09-01), None
patent: 1085577 (2001-03-01), None
patent: 0 193 765 (2002-04-01), None
patent: 61-156882 (1986-07-01), None
patent: 63-054762 (1988-03-01), None
patent: 63-205927 (1988-08-01), None
patent: 2-091974 (1990-03-01), None
patent: 4-162573 (1992-06-01), None
patent: 5-109883 (1993-04-01), None
patent: 08255902 (1996-10-01), None
patent: WO - 98/33218 (1998-07-01), None
patent: WO - 02/27800 (2002-04-01), None
Yoshino, Hideo et al., “A 70-V, 90-momega mm2, High-Speed Double-Layer Gate UMOSFET Realized by Selective CVD Tungsten”, Proceedings of the International Symposium on Power Semiconductor Devices (ISPSD), Davos, Switzerland, May 31-Jun. 2, 1994, New York, IEEE, vol. Symp. 6, May 31, 1994, pp. 365-369.
Wolf, Stanley et al., “Silicon Processing for the VLSI Era, vol. 1: Process Technology”, 1986, Lattice Press, Sunset Beach, California.
Kim, Han-Soo et al., “Breakdown Voltage Enhancement of the p-n Junction by Self-Aligned Double Diffusion Process Through a Tapered SiO2Implant Mask”, IEEE Electron Device Letters, Sep. 1995, vol. 16, No. 9.
Yano, Koji et al., “Application of a Junction Field Effect Transistor Structure to a Low Loss Diode”, Jpn. J. Appl. Phys., Mar. 1997, vol. 36, Part 1, No. 3B.
Nam, K.S. et al., “Very high density trench gate power MOSFET using simplified four-mask process”, Electronics Letters, Nov. 25, 1999, vol. 35, No. 24.
Narazaki, A. et al., “A 0.35um Trench Gate MOSFET with an ultra low on state resistance and a high destruction immunity during the inductive switching”, ISPSD, May 22-25, 2000, Toulouse, France.
Kim, Jongdae et al., “High-Density Low On-Resistance Trench MOSFETs Employing Oxide Spacers and Self-Align Technique for DC/DC Converter”, ISPSD, May 22-25, 2000, Toulouse, France.
Nam, Kee Soo et al., “A Novel Simplified Process for Fabricating a Very High Density P-Channel Trench Gate Power MOSFET”, IEEE Electron Device Letters, Jul. 2000, vol. 21, No. 7.
Zeng, Jun et al., “An Ultra Dense Trench-Gated Power MOSFET Technology Using A Self-Aligned Process”, Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs, 2001, Osaka, Japan.
Finney, Adrian et al., “Recessed Trench MOSFET Process Without Critical Alignments Makes Very High Densities Possible”, Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs, 2001, Osaka, Japan.
Peake, Steven T. et al., “Fully Self-Aligned Power Trench-MOSFET Utilising 1um Pitch and 0.2um Trench Width”, IEEE, 2002.
Heuting, R.J.E. et al., “Switching Performance of Low-Voltage N-Channel Trench MOSFETs”, IEEE, 2002.
Fujishima, Naoto et al., “A High-Density Low On-Resistance Trench Lateral Power MOSFET With a Trench Bottom Source Contact”, IEEE Transactions on Electron Devices, Aug. 2002, pp. 1462-1468, vol. 49, No. 8.

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