Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-09-14
2003-09-09
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S014000
Reexamination Certificate
active
06618837
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the simulation of electronic circuits and, more particularly, to the high frequency modeling of MOSFET circuit elements.
2. Background Information
MOSFET technology was originally developed for use in DC and low frequency applications. As early versions of this technology were incapable of operating properly at higher frequencies, bipolar junction and GaAs transistors were used for radio frequency applications. However, as MOSFET process technology has moved into the deep submicron region, the cut-off frequencies of such devices has increased into the tens of gigahertz, making MOSFET technology a serious alternative for high frequency circuit integration.
The use of entirely MOSFET technology for implementing circuits for radio frequency applications allows for maximum integration of the RF front end, baseband logic, custom analog, and memory modules for complete systems on a single chip. Integration not only reduces device size, but allows system manufacturers to drive manufacturing costs down.
An important tool in the design of such large integrated circuits are methods of circuit simulation, the most familiar being SPICE. To run a SPICE or other circuit simulation, the circuit designer provides a description of the circuit, choosing a model for the various elements and specifying the parameter values, and the desired analysis, which specifies what sort of simulation will be performed in order to provide the desired output. This information forms a netlist which the designer runs to analyze the circuit.
The simulation tools available for non-linear MOSFET devices reflect the origin of this technology in DC and low frequency applications. While MOSFET devices now possess the performance needed for high frequency operation, the available design tools have yet to fully learn and embrace the intricate physical phenomena of such high speeds of operation. Without access to such “RF-ready” design tools, designers are hard pressed to design products that meet the tight constraints on power consumption and noise that leave very little margin for error.
One technique used in simulation is to replace non-linear elements in the netlist with a sub-circuit. Although it is possible to use a detailed equivalent circuit that accounts for all the physical elements that are part of a MOSFET transistor operating at high frequencies, the result is generally too complex to implemented as a compact model or sub-circuit for simulation. Additionally, many of the component values would be difficult or even impossible to extract and the resultant sub-circuit would contain a large number of internal nodes, greatly increasing the simulation time. Current techniques for the production of a sub-circuit for use in simulation of MOSFET circuits are extremely slow and often provide inaccurate results when pushed into the RF region. What is required is a MOSFET model that can accurately extend well into the gigahertz range, be quick, and still give accurate DC and low frequency AC fitting.
Another important consideration in circuit design is noise. In addition to providing a unified design tool that can accurately describe MOSFET operation in the DC region as well as its high frequency behavior, the model should preferably incorporated noise considerations. In this way, the designer can simultaneously consider all of these effects and emphasize those most important to overall circuit's characterization.
SUMMARY OF THE PRESENT INVENTION
The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing models that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes.
According to one aspect of the present invention, the method for modeling MOSFETs incorporates the device's high frequency characterizations while still maintaining an accurate DC and low frequency AC description. In the exemplary embodiment, this process begins with receiving DC characterizations of the device, such as terminal current vs. terminal voltage and terminal capacitance vs. terminal voltage. The resultant DC modeling can accurately predicate the low frequency characterizations and is converted into a sub-circuit which contains a intrinsic MOSFET and some parasitic elements. The topology of this sub-circuit is user definable. The S parameters of the device are also measured and are used in a de-embedding process to eliminate the parasitic effects. Physical extraction determines initial values for the sub-circuit elements. Once these values are set, the simulated device high frequency characterization is compared with measured characterization from the S parameters. An optimization procedure is used to reduce the difference between simulated and measured characterization by adjusting user selected model parameters, value of elements in sub-circuit, or a combination of both.
In an exemplary embodiment, when the DC model is converted into a sub-circuit, several key model parameters are checked, such as the source to drain resistance, R
dsw
If the resultant parameter values in model card are too big, then this model card is not readily adapted to the present process, or is not “RF-ready”, and the DC model may need to be regenerated. Another example of a parameter which may be checked is the source to drain junction capacitance, C
jswg
, possibly resulting in a pair of external diode elements being extracted and added to the sub-circuit, with one at the source terminal and the other at the drain terminal.
According to another aspect of the present invention, an improved method of simulating the device's response parameters is described which allows a user to optimize the sub-circuit more quickly. This is done by greatly reducing the number of iterations needed during this process. A simulation engine calculates the response of the device in Y parameter representation and subsequently converts them into S parameters. Additionally, not all data points are simulated: only a subset of these points are simulated with the rest interpolated. This allows the simulation to be performed in real time, allowing for an interactive optimization.
Another feature of the present invention optimizes the DC characterizations and high frequency characterization of the device simultaneously. As the high frequency characterization is a strong function of first derivative of the drain current, the model can no longer just fit the drain current, but must also fit its derivative. Due to the limitations of modelling, some trade off between DC fitting error and high frequency fitting error is usually necessary. By allowing the user to choose the targets for the optimization process, the user can perform a multi-object optimization and balance the relative importance of the DC and high frequency characterizations.
The present invention also provides a graphic user interface for performing the optimization process. The interface allows the user to select model parameters or elements within the sub-circuit, vary their values, and dynamically present the change of the simulated DC and high frequency characterizations. This provides an intuitive way to analysis the sensitivity of these parameters.
Further aspects of the present invention extend its methods to incorporate RF noise modeling. In one embodiment, after the high frequency model has been created, the measured minimum noise figure and optimum matching impedance are received after de-embedding. Physical extraction is performed and noise data is simulated and compared with measured data. Optimization is then performed to reduce the difference between the simulated and measured data. The optimization can again be done with the graphic user inter
Guo Jianhe
Liang Hancheng
Liu Zhihong
Zhang Xisheng
Cadence Design Systems Inc.
Niebling John F.
Parsons Hsue & de Runtz LLP
Whitmore Stacy
LandOfFree
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