MOSFET having a double gate

Details MOSFET having a double gate MOSFET having a double gate

2002-02-21

2003-11-11

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S366000, C257S368000

Reexamination Certificate

active

06646307

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and the fabrication thereof and, more particularly, to a MOSFET having a double gate and a method of formation.
BACKGROUND
A pervasive trend in modern integrated circuit manufacture is to produce semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), that are as small as possible. In a typical MOSFET, a source and a drain are formed in an active region of a semiconductor layer by implanting N-type or P-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer. It is noted that MOSFETs can be formed in bulk format (for example, the active region being formed in a silicon substrate) or in a semiconductor-on-insulator (SOI) format (for example, in a silicon film that is disposed on an insulating layer that is, in turn, disposed on a silicon substrate).
Although the fabrication of smaller transistors allows more transistors to be placed on a single monolithic substrate for the formation of relatively large circuit systems in a relatively small die area, this downscaling can result in a number of performance degrading effects. For example, certain materials, when used in a down-scaled device, may become electrically leaky and can cause reliability problems.
Another trend in modern integrated circuit manufacture is to produce high performance semiconductor devices with low threshold voltages, low power consumption and increased switching speed. For example, SOI devices have been shown to have enhanced device performance over bulk devices due to a variety of desirable characteristics. However, an increase in performance beyond that currently attainable in SOI devices is desirable.
Accordingly, there exists a need in the art for semiconductor devices, such as MOSFETs, that optimize scale and performance. There also exists a need for corresponding fabrication techniques to make those semiconductor devices.
SUMMARY OF THE INVENTION
According to one aspect of the invention, a double gate MOSFET is provided. The MOSFET includes a bottom gate having a bottom gate electrode and a bottom gate dielectric formed from a high-K material disposed over the bottom gate electrode. The MOSFET also includes a semiconductor body region disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate including a top gate electrode is disposed over the body. A top gate dielectric separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain.
According to another aspect of the invention, a double gate MOSFET is provided. The MOSFET includes a bottom gate including a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. The MOSFET also includes a semiconductor body region disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate including a top gate electrode is disposed over the body. A top gate dielectric formed from a high-K material separates the top gate electrode and the body, the top gate electrode and the bottom gate electrode defining a channel within the body and interposed between the source and the drain.
According to yet another aspect of the invention, a method of forming a double gate MOSFET. The method includes providing wafer, the wafer including a semiconductor substrate having an insulating layer disposed over the semiconductor substrate; forming a bottom gate electrode over the insulating layer; forming a bottom gate dielectric over the bottom gate electrode; forming a seeding window in at least the insulating layer to expose a portion of the semiconductor substrate; forming a semiconductor body region over the bottom gate electrode and separated from the bottom gate electrode by the bottom gate dielectric; and forming a top gate having a top gate electrode over the body region, the top gate electrode and the body region separated by a top gate dielectric. The step of forming the semiconductor body region includes forming an amorphous semiconductor film on the wafer and over the bottom gate dielectric and recrystallizing the amorphous semiconductor film using the semiconductor substrate as a seed crystal.


REFERENCES:
patent: 5604368 (1997-02-01), Taur et al.
patent: 5689127 (1997-11-01), Chu et al.
patent: 5773331 (1998-06-01), Solomon et al.
patent: 5780327 (1998-07-01), Chu et al.
patent: 6013553 (2000-01-01), Wallace et al.
patent: 6020024 (2000-02-01), Maiti et al.
patent: 6166412 (2000-12-01), Kim et al.
patent: 6335214 (2002-01-01), Fung
patent: 6403981 (2002-06-01), Yu
patent: 6514826 (2003-02-01), Park et al.
patent: 408321617 (1996-12-01), None

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