MOSFET fabrication method

Details MOSFET fabrication method MOSFET fabrication method

2002-06-10

2004-04-27

Ho, Hoai (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S162000, C438S163000, C438S270000, C438S479000, C438S517000, C438S589000, C257S077000, C257S607000, C257S612000, C257S617000

Reexamination Certificate

active

06727147

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a method of fabricating a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), and more particularly to a method of forming a field oxide film which provides hyperfine device isolation on a Silicon-on-Insulator (SOI) substrate by means of Local Oxidation of Silicon (LOCOS).
2. Description of the Related Art
With the recent remarkable progress in semiconductor devices, demand is increasing for an LSI on which both digital and analog circuits are mounted, and which performs at high speed and with reduced power consumption. To meet this demand, semiconductor devices are required to be integrated more densely. As the devices to be mounted increase in number, isolation regions must be narrower and smaller.
A conventional method of fabricating a MOSFET in an SOI substrate by means of LOCOS is illustrated in
FIGS. 2A-2F
, each of which schematically shows a cross-section of the MOSFET at a fabrication step. Descriptions of the steps are as follows:
a) A pad oxide film
52
of about 5-10 nm is deposited on an SOI substrate
51
. Then an active nitride film
53
of about 50-150 nm is deposited on the pad oxide film
52
as an oxidation-resistant mask (see FIG.
2
A).
b) Openings are formed in the laminated layers of the pad oxide film
52
and the active nitride film
53
at positions where field oxide films
54
are to be provided, by a conventional lithography technique (see FIG.
2
B).
c) The field oxide films
54
are formed on the SOI substrate
51
by dry oxidation (a heat treatment conducted in a dry oxygen atmosphere) (see FIG.
2
C).
d) The remaining portions of the active nitride film
53
and the pad oxide film
52
are removed (see FIG.
2
D).
e) Gate electrodes
55
are provided by a conventional process for fabricating MOSFETs (see FIG.
2
E).
f) SiO
2
side walls
57
are formed by first providing an SiO
2
film on the substrate and then etching back. Impurities are then introduced into the substrate by means of ion implantation to form source/drain regions
58
. Finally, the impurities in the source/drain regions
58
are activated by RTA (rapid thermal annealing) and a MOSFET with low source/drain resistance is obtained (see FIG.
2
F).
In the above-described conventional method, when the width of a field oxidation region (i.e., the distance between adjacent devices (Wi in FIG.
2
B)) is reduced to 0.2 &mgr;m or less (“sub-quarter micron”), there arises a problem of insufficiency of an oxidation amount in the dry oxidation process and a resultant insufficiency in thickness of the thermal oxidation film. One of the reasons for this insufficiency in the oxidation amount is stress generated in the SOI substrate at the time of forming the openings for the field oxidation regions (in the step b).
To obtain a sufficient amount of oxidation, an oxidizing temperature may be increased and oxidizing time may be lengthened. However, thermal oxidation at a high temperature for a long time will cause stress in the whole SOI substrate (i.e., in the wafer). This stress may induce defects in crystals in the substrate or cause warping of the substrate. Thus, if the oxidation is conducted at high temperature for a long time to ensure a sufficient amount of oxidation in hyperfine isolation regions of about 0.2 &mgr;m, the amount of oxidation will be excessively increased at areas where the design rules are less strict (e.g., peripheral circuits); i.e., the device isolation regions at those areas may be relatively wide. The thickness of the silicon layer of the SOI substrate is thinner than the conventional silicon substrate (silicon wafer). For example, the typical thickness of the silicon layer of the SOI substrate is about several nm, while the typical thickness of the conventional silicon substrate is, for example, about 625 &mgr;m. Therefore, the increase of amount of oxidation may significantly cause stress in the peripheral circuit regions of the LSI, in particular, formed in the SOI, and thus cause increases in leakage currents, for example. Such effects may adversely affect the operating characteristics of the LSI which is formed on an SOI substrate.
SUMMARY OF THE INVENTION
In view of the aforementioned, an object of the present invention is to obtain a sufficient amount of oxidation, without changing oxidation conditions such as temperature or time, during forming of device isolation regions of 0.2 &mgr;m or less by thermal oxidation.
To achieve the above object, a first aspect of the present invention is a method of fabricating a MOSFET, the method comprising:
(a) preparing an SOI substrate;
(b) depositing an oxide film on the SOI substrate;
(c) depositing a nitride film on the oxide film;
(d) forming an opening in the nitride film and oxide film at a predetermined region, at which a device isolation region is to be formed, by lithography for exposing a surface of the SOI substrate;
(e) irradiating the substantially the entire area of the silicon substrate with Ar ions;
(f) forming a field oxide film by dry oxidation; and
(g) removing remaining portions of the nitride film and the oxide film.
In a second aspect of the present invention, Si ions are used in place of the Ar ions in the first aspect.
A third aspect of the present invention is a method for fabricating a MOSFET, the method comprising:
(a) preparing an SOI substrate having a structure of silicon layer/buried oxide/substrate;
(b) depositing an oxide film on the SOI substrate;
(c) depositing a nitride film on the oxide film;
(d) forming an opening in the nitride film and oxide film at a predetermined region, at which a device isolation region is to be formed, by lithography for exposing a surface of the SOI substrate;
(e) irradiating substantially the entire area of the SOI substrate with at least one of Ar ions and Si ions for implanting the at least one of Ar ions and Si ions into the silicon layer of the SOI substrate in the vicinity of the surface exposed by the step of forming the opening, the nitride film and the oxide film serving as a mask;
(f) forming a field oxide film by dry oxidation; and
(g) removing remaining portions of the nitride film and the oxide film.
In each aspect, the thickness of the oxide film is preferably about 5-10 nm, and the thickness of the oxidation-resistant nitride film provided on the oxide film is preferably about 50-150 nm. The ion implantation is preferably conducted at an implantation energy of 40-50 keV, and implantation dose of 1×10
14
to 5×10
15
cm
−2
.
Through the ion implantation under these conditions, the regions of the substrate where the openings are formed become amorphous, while defects in the substrate at the regions where devices are to be mounted can be avoided. Therefore, the field oxidation is enhanced, and the thickness of the thermal oxidation film will be sufficient even at the device isolation regions having openings of 0.2 &mgr;m or less. Further, no harmful effects will be caused to the electric characteristics of the device.


REFERENCES:
patent: 6075259 (2000-06-01), Baliga
patent: 6210998 (2001-04-01), Son
patent: 6228691 (2001-05-01), Doyle
patent: 6429055 (2002-08-01), Oh
patent: 11-087336 (1999-03-01), None

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