Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-22
2002-01-29
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S305000, C438S230000
Reexamination Certificate
active
06342423
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing MOS-type transistor devices and semiconductor integrated circuits with improved processing methodology resulting in increased reliability and quality, increased, manufacturing throughout, and reduced fabrication cost. The present invention is also useful in the manufacture of CMOS semiconductor devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 &mgr;m, e.g., about 0.15 &mgr;m.
BACKGROUND OF THE INVENTION
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires design features of 0.18 &mgr;m and below, such as 0.15 &mgr;m and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 &mgr;m and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so-called “short-channel” effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and the drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, lightly- or moderately-doped source/drain extension-type transistor structures have been developed, as described below.
For p-channel MOS transistors of short-channel type, the major limitation on performance arises from “punch-through” effects which occur with relatively deep junctions. In such instances, there is a wider subsurface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned “punch-through” current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS devices is the provision of light- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped drain region in internally disposed away from the gate by use of a sidewall spacer on the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
Several processing sequences or schemes have been developed for the manufacture of source/drain extension-type MOS and CMOS transistors for use in high-density integration applications, with a primary goal of simplifying the manufacturing process by reducing and/or minimizing the number of processing steps. Conventional processing schemes for making such MOS transistors generally employ disposable spacers made of various materials, e.g., polysilicon, silicon oxides, silicon nitrides, silicon oxynitrides, and combinations thereof.
According to one conventional process scheme, a precursor structure comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and on overlying gate electrode formed on a portion of a surface thereof is subjected to ion implantation prior to sidewall formation for forming lightly- or moderately-doped implants therein. Following post-implantation annealing, sidewall spacers are formed on the pair of opposing side surfaces of the layer stack by first depositing a dielectric spacers material layer over the substrate surfaces and then removing same from the horizontal regions, i.e., the top surface of the gate electrode layer, and the source and drain regions, by anisotropically etching. Such processing results in sidewall spacers left on the gate layer stack side surfaces that have an approximately quarter-circular cross-section. The dielectric sidewall spacers typically remain through the balance of junction formation processing. After sidewall spacer formation, a heavy source/drain implantation is performed, with the gate layer stack and associated sidewall spacers acting as implantation masking materials. As a consequence of the separate implantations, the heavily-doped source/drain regions are laterally displaced from the gate edges by the thickness of the sidewall spacer material and the lightly- or moderately-doped regions beneath the sidewall spacers act as source/drain extensions.
According to another conventional process scheme, which scheme employs disposable (i.e., removable) spacers, a precursor structure as described above and comprising a semiconductor substrate of one conductivity type having a layer stack comprising a thin gate oxide layer and an overlying gate electrode layer formed on a portion of a surface thereof is subjected to dielectric layer deposition and patterning to form sidewall spacer layers on opposing side surfaces of the layer stack. Opposite conductivity type P- and N- type dopant impurities are then implanted into the substrate using the layer stack with sidewall spacers formed thereon as an implantation mask to form moderately to heavily-doped implants. High temperature annealing is then performed to thermally activate the implanted dopant by diffusion and reduce lattice damage due to implantation, thereby forming source/drain regions and junctions at a predetermined dopant density and depth below the substrate surface. The effective length of the channel length of such transistors is determined by the width of the gate insulator/gate electrode layer stack and the width of the sidewall spacers formed thereon. After activation annealing, the sidewall spacers are removed, as by etching, and a second implantation process for implanting N- or P-type opposite conductivity type dopant impurities is performed using only the gate insulator layer/gate electrode layer stack as an implantation mask, thereby forming shallow-depth, lightly- or moderately-doped intermediate implants in the substrate in the spacers between the deeper, more heavily-doped source/drain region. Following the implantation, a second activation process, e.g., rapid thermal annealing (RTA), is performed for effecting dopant diffusion and relaxation of implantation induced lattice damage of the intermediate implants, to form shallow-depth, lightly- or moderately-doped source/drain extensions extending from respective proximal edges of the heavily-doped source/drain regions to just below the respective proximal edges of the gate insulator layer/gate electrode layer stack.
The above-described process, which employs removable sidewall spacers as part of the implantation mask for defining the channel lengths, incurs a drawback in that the materials conventionally used for the sidewall spacers, such as those enumerated above, are frequently difficult and time consuming to remove by standard etching methodologies. For example, and as described in U.S. Pat. No. 5,766,991, removal of silicon nitride-based spacer layers can require etching in a hot phosphoric acid (H
3
PO
4
) bath at about 180° C. for approximately 1.5 hours. Such long etching time results in reduced manufacturing throughput and the extended exposure to and concomitant attack by the corrosive reagent at high temperature results in undesired etching and defect formation. Moreover, portions of the workpiece substrate not intended to be etched must be provided with an etch-resistant protective barrier layer, e.g. of silicon oxide, prior to etching. However, the etching resistance to the hot phosphoric acid of the silicon oxide layer itself may be insufficient, in which case the resistance thereof must be increased prior
Hao Ming Yin
Ibok Effiong
Ishida Emi
Krishnan Srinath
Advanced Micro Devices , Inc.
Lindsay Jr. Walter L.
Niebling John F.
LandOfFree
MOS-type transistor processing utilizing UV-nitride... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS-type transistor processing utilizing UV-nitride..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS-type transistor processing utilizing UV-nitride... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2832093