MOS transistors with raised sources and drains

Details MOS transistors with raised sources and drains MOS transistors with raised sources and drains

2001-06-20

2002-08-06

Lebentritt, Micheal S. (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S300000, C438S424000, C438S479000, C438S589000

Reexamination Certificate

active

06429084

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention is submicron MOS circuit processing with raised source/drain structures.
BACKGROUND OF THE INVENTION
In forming raised source-drain (S/D) transistors in submicron dimensions, a problem has arisen—that the polysilicon (poly) gate acts as a base for epitaxial growth as well as the exposed silicon in the S/D region. The epitaxial silicon (epi) in the gate expands laterally and not only physically blocks portions of the S/D, but also causes variation in device characteristics along the length of the transistor because of interference between the expanded gate and the S/D extension implant.
In addition, the preclean step that is required to remove oxide before the epi growth can overetch the shallow trench isolation (STI) fill, exposing silicon during the epi growth step. With this unwanted epi at or near the isolation, there is a potential for shorting across the isolation.
SUMMARY OF THE INVENTION
The invention relates to a method of transistor formation that provides a protective layer over the gate and over the STI during the epi growth step, thereby preventing unwanted epi growth on the gate and/or in the isolation.
A feature of the invention is the formation of temporary poly sidewalls that are removed before the S/D implantation, so that the extension and/or halo implants are performed after the S/D implant, and preferably after the S/D anneal.
Another feature of the invention is forming an oxide
itride/oxide sandwich layer on top of the poly so the poly top surface is not exposed during the removal of the temporary poly sidewall spacer.
Yet another feature of the invention is damaging the protective layer by ion implantation before its removal.


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patent: 6204138 (2001-03-01), Krishnan et al.
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patent: 2001/0044188 (2001-11-01), Heo et al.
patent: 2002/0011617 (2002-01-01), Kubo et al.

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