Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2001-01-31
2002-10-01
Jackson, Jerome (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S264000, C438S287000, C438S770000, C438S981000, C438S179000, C257S336000
Reexamination Certificate
active
06458639
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication, and more particularly to methods for fabricating improved ultra-large scale integration (ULSI) semiconductor devices such as ULSI metal oxide silicon field effect transistors (MOSFETs).
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer. This generally-described structure cooperates to function as a transistor.
To facilitate cooperation between the gate and the source and drain regions, most of the source and drain regions do not lie directly under the gate. However, a small part of the source region does overlap the gate, and likewise a small part of the drain region extends directly under the gate. These small parts of the source and drain regions that overlap the gate are respectively referred to as the source and drain extensions.
While the present invention understands that such extensions enhance the coupling between the gate and the channel that is established by the source and drain regions, the present invention also understands that capacitive coupling is induced between the gate and the source/drain extensions. As recognized herein, such capacitive coupling degrades the performance of the transistor in alternating current (AC) applications. The importance of this consideration grows as the size of the transistors is reduced by ULSI technology, because while the overall dimensions of the transistors are smaller (and in particular the gate length), the amount by which the source/drain extensions overlap the gate have heretofore remained unchanged. Accordingly, the ratio between the amount of overlap to gate length is increased as gate length is shortened, thus magnifying the undesirable effects of capacitive coupling between the gate and the source/drain extensions in very small transistors.
Moreover, owing to the very small thickness of the insulating gate oxide layer between the gate and the source/drain extension regions, and the relatively high electric field across the gate oxide layer, charge carriers undesirably can tunnel across the gate oxide layer. This renders the transistor “leaky”, degrading its performance. Accordingly, the present invention understands that it is desirable to minimize the overlap between the gate of a transistor and the source/drain extension regions of the transistor.
One approach to the above-noted problem would be to simply space apart the source and drain regions from each other and, hence, reduce the overlap between the source/drain extensions and the gate. This could be done by forming the gate, then forming spacers on the side of the gate, and then implanting dopant into the substrate to establish the source and drain, with the spacers blocking the implantation of dopant in the substrate near the sides of the gate. As recognized herein, however, a drawback of such a process is that the channel length would be enlarged. An enlarged channel length in turn would reduce the transistor drive current and thereby reduce the speed of operation of the circuit.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for forming one or more field effect transistors (FET) on a semiconductor substrate. The method includes forming a lower gate insulator on the substrate, and the lower gate insulator defines a length and is substantially continuous along the length. An upper gate insulator is formed on the lower gate insulator such that the upper gate insulator is not substantially continuous along the length and such that a gate step is established by the lower and upper insulators. Then, a gate electrode is formed on the gate insulators. In a preferred embodiment, the lower gate insulator includes nitride, and the upper gate insulator includes oxide.
In a preferred embodiment of the present method, the gate insulators are initially formed as continuous layers, and a gate is formed above the gate insulators. Source and drain regions are then established in the substrate, with the source and drain regions respectively having source and drain extensions that extend under the gate. Also, a field oxide layer is formed on the substrate adjacent the gate. The gate is then removed to establish a gate void above the gate insulators, and one or more spacers are formed adjacent the wall in the gate void. As intended by the present invention, the spacers cover only a shielded portion of the upper insulator, and do not cover an unshielded portion of the upper insulator. Accordingly, the unshielded portion can be removed by etching, to thereby establish the gate step prior to the forming of the gate electrode on the gate insulators. The spacers are configured such that the gate step is substantially directly above the source and drain extensions, to suppress capacitive coupling between the gate electrode and the source/drain extensions. A semiconductor device made in accordance with the present method, and a digital processing apparatus incorporating the semiconductor device, are also disclosed.
In another aspect, a method for making a semiconductor device includes depositing at least upper and lower gate insulators on a semiconductor substrate, and depositing at least one field oxide layer above the substrate. Also, the method includes establishing at least one gate void in the field oxide layer. Moreover, the method includes removing only a portion of the upper gate insulator in the gate void, and then filling the gate void with a field effect transistor gate material.
In yet another aspect, a semiconductor device includes at least one field effect transistor (FET) defining a gate disposed above a silicon substrate and source and drain regions in the silicon substrate. Per the present invention, the source and drain regions include source and drain extensions that are separated from each other by a substantially undoped channel region. Plural layers of gate insulator material are disposed between the gate and the extensions, with only a single layer of gate insulator material being disposed between the gate and the channel region.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
REFERENCES:
patent: 5445983 (1995-08-01), Hong
patent: 5716861 (1998-02-01), Moslehi
patent: 5960270 (1999-09-01), Misra et al.
patent: 6077749 (2000-06-01), Gardner et al.
patent: 6200843 (2001-03-01), Bryant et al.
An Judy Xilin
Lin Ming-Ren
Yu Bin
Advanced Micro Devices , Inc.
Jackson Jerome
LaRiviere Grubman & Payne, LLP
Rao Shrinivas H.
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