Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-09-17
2001-07-24
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S230000, C257S387000
Reexamination Certificate
active
06265256
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication, and more particularly to methods for fabricating improved ultra-large scale integration (ULSI) semiconductor devices such as ULSI metal oxide silicon field effect transistors (MOSFETs).
BACKGROUND OF THE INVENTION
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital camareras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer. This generally-described structure cooperates to function as a transistor.
To facilitate cooperation between the gate and the source and drain regions, most of the source and drain regions do not lie directly under the gate. However, a small part of the source region does overlap the gate, and likewise a small part of the drain region extends directly under the gate. These small parts of the source and drain regions that overlap the gate are respectively referred to as the source and drain extensions.
While the present invention understands that such extensions enhance the coupling between the gate and the channel that is established by the source and drain regions, the present invention also understands that capacitive coupling is induced between the gate and the source/drain extensions. As recognized herein, such capacitive coupling degrades the performance of the transistor in alternating current (AC) applications. The importance of this consideration grows as the size of the transistors is reduced by ULSI technology, because while the overall dimensions of the transistors are smaller, the amount by which the source/drain extensions overlap the gate have heretofore remained unchanged. Accordingly, the undesirable effects of capacitive coupling between the gate and the source/drain extensions are magnified in very small transistors.
Moreover, owing to the very small thickness of the insulating gate oxide layer between the gate and the source/drain extension regions, and the relatively high electric field across the gate oxide layer, charge carriers undesirably can tunnel across the gate oxide layer. This renders the transistor “leaky”, degrading its performance. Accordingly, the present invention understands that it is desirable to minimize the overlap between the gate of a transistor and the source/drain extension regions of the transistor.
One approach to the above-noted problem would be to simply space apart the source and drain regions from each other and, hence, reduce the overlap between the source/drain extensions and the gate. This could be done by forming the gate, then forming spacers on the side of the gate, and then implanting dopant into the substrate to establish the source and drain, with the spacers blocking the implantation of dopant in the substrate near the sides of the gate. As recognized herein, however, a drawback of such a process is that the channel length would be enlarged. An enlarged channel length in turn would reduce the transistor drive current and thereby reduce the speed of operation of the circuit.
BRIEF SUMMARY OF THE INVENTION
A method is disclosed for forming one or more field effect transistors (FET) on at least one semiconductor substrate. The method includes establishing a source region in the substrate, with the source region having a source extension. Also, a drain region having a drain extension is established in the substrate, and gate spacers are disposed above the source and drain extensions. A gate electrode is disposed between the gate spacers, such that the gate electrode substantially does not overlap the source and drain extensions. With this structure, the length of the gate electrode is precisely established, and fringe coupling between the gate electrode and the source and drain extensions is suppressed.
Preferably, a gate insulator is disposed between the gate electrode and the substrate. At least one field oxide layer is formed on the substrate, with at least one gate void being formed in the field oxide layer. As disclosed in detail below, the gate void defines at least one wall. The gate electrode is formed in the gate void and is spaced from the wall of the void.
The preferred method for forming the gate void includes forming a gate oxide on the substrate, followed by forming a gate polysilicon on the gate oxide. The field oxide layer is established around the gate polysilicon. The gate polysilicon is then removed to establish the gate void.
In a particularly preferred embodiment, the gate spacers include nitride. When the spacers are made of nitride, the method further includes depositing a protective oxide layer between the gate spacers and the gate electrode. A semiconductor device made in accordance with the present method, and a digital processing apparatus incorporating the semiconductor device, are also disclosed.
In another aspect, a method for suppressing fringe coupling between a gate electrode of a semiconductor device and source and drain extensions in operative cooperation with the gate electrode includes establishing at least one gate void defining a wall above a semiconductor substrate. Moreover, the method includes disposing at least one nitride gate spacer in the gate void against the wall. Further, the method contemplates disposing at least one gate electrode in the gate void such that the gate spacer is disposed between the wall and the gate electrode. At least one protective oxide layer is positioned between the nitride gate spacer and the gate electrode, and at least one gate insulator is disposed between the gate electrode and the substrate.
In still another aspect, a method for making one or more ULSI MOSFETs having suppressed fringe coupling between transistor gates and associated transistor sources and drains includes establishing a source region in a semiconductor substrate, with the source region having a source extension. Also, a drain region is established in the substrate, with the drain region having a drain extension. Next, at least one gate void defining a wall is established above the substrate, with at least one gate spacer being disposed in the gate void against the wall above one or more of the source extension and drain extension. The method further includes disposing at least one gate electrode in the gate void such that the gate spacer is disposed between the wall and the gate electrode. With these features, the gate electrode substantially does not overlap the source and drain extensions, and fringe coupling between the gate electrode and the source and drain extensions consequently is suppressed.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
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paten
An Judy Xilin
Liu Yowjuang W.
Yu Bin
Advanced Micro Devices , Inc.
Chaudhuri Olik
LaRiviere Grubman & Payne, LLP
Peralta Ginette
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