Mos transistor with dual pocket implant

Details Mos transistor with dual pocket implant Mos transistor with dual pocket implant

1999-06-15

2001-07-03

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S305000, C438S525000, C438S527000

Reexamination Certificate

active

06255174

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to MOSFET devices. Even more particularly, the present invention relates to ULSI MOSFET devices with a delayed threshold voltage roll-off.
BACKGROUND OF THE INVENTION
As the critical dimensions (CD) of ULSI MOSFET's keep shrinking, the channel doping profile becomes more critical. A good channel profile provides excellent immunity to short-channel effects, such as threshold voltage (V
th
) roll-off and drain-induced-barrier-lowering, making the device very robust to random process variation (especially, gate length (L
g
) variation). In a MOSFET with a uniformly doped channel (without channel doping engineering), the threshold voltage V
th
drops rapidly as gate length L
g
is reduced. In a MOSFET with conventional halo or pocket implant, the V
th
roll-off is delayed to some degree due to a “reverse short-channel effect” or “V
th
roll-up.” The V
th
roll-up occurs because the “effective” or average channel doping concentration is raised as result of closer pocket peaks in the channel as the gate length L
g
gets shorter. However, when the two peaks of the pockets from the source side and drain side completely merge together, the average channel doping concentration no longer increases as L
g
decreases. Therefore, the threshold voltage V
th
starts to drop rapidly due to short-channel effects.
BRIEF SUMMARY OF THE INVENTION
It is an object of the invention to delay the rapid roll-off of the threshold voltage V
th
so that the threshold voltage V
th
drop occurs at a smaller gate length L
g
.
It is another object of the invention to delay threshold voltage V
th
roll-off as gate length L
g
is reduced.
Accordingly, the foregoing objects are accomplished by creating a semiconductor device, comprising: a substrate with a surface; a gate oxide on the surface of the substrate; a gate on the gate oxide; a dielectric spacer adjacent to the gate oxide, the gate and the substrate; a source pocket extending into the substrate and under the oxide gate and on a source side of the gate, comprising: a first source dopant pocket extending into the substrate and under the dielectric spacer and oxide gate; and a second source dopant pocket extending under the dielectric spacer and further into the substrate and further under the oxide gate than the first source dopant pocket; a drain pocket extending into the substrate and under the dielectric spacer and the oxide gate and on a drain side of the gate, consisting of one and only one drain dopant pocket; a source extension extending into the substrate and under the dielectric spacer and the oxide gate on the source side of the gate; and a drain extension extending into the substrate and under the dielectric spacer and oxide gate on the drain side of the gate.
Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION.”


REFERENCES:
patent: 5364807 (1994-11-01), Hwang
patent: 5372957 (1994-12-01), Liang et al.
patent: 5510279 (1996-04-01), Chien et al.
patent: 5716866 (1998-02-01), Dow et al.
patent: 5759901 (1998-06-01), Loh et al.
patent: 5776806 (1998-07-01), Dennison et al.
patent: 5830788 (1998-11-01), Hiroki et al.
patent: 5926712 (1999-07-01), Chen et al.
patent: 5960291 (1999-09-01), Krivokapic
patent: 6022785 (2000-02-01), Yeh et al.
patent: 6063673 (2000-05-01), Kao et al.
patent: 6107129 (2000-09-01), Gardner et al.
Bin Yu et al, Reverse Short-Channel Effects & Channel-Engineering in Deep-Submicron MOSET's : Modeling and Optimization, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 162 & 163.
Bin Yu et al, Short-Channel Effect Improved by Lateral Channel-Engineering in Deep-Submicronmeter MOSET's, IEEE: Transactions on Electron Devices, vol. 44, No. 4, Apr. 1997, pp. 627-634.

Affiliated with

Also associated with

Rating

Mos transistor with dual pocket implant does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mos transistor with dual pocket implant, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mos transistor with dual pocket implant will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2559686