Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-30
2001-03-13
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S424000, C438S429000, C257S362000, C257S330000, C257S497000
Reexamination Certificate
active
06200841
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for fabricating semiconductor devices, and more particularly, to a MOS transistor and a method for fabricating the same.
2. Description of the Related Art
FIG. 1
shows a conventional MOS transistor. The conventional MOS transistor includes a P or N-type semiconductor substrate
1
, a well region
3
formed in the semiconductor substrate
1
doped with impurities having conductivity opposite to those doped in the substrate
1
, and isolation regions
2
realized by forming openings in the semiconductor substrate
1
and filling the openings with an oxide material (e.g. silicon oxide).
Formed over a “channel portion” of the well region
3
are a gate oxide layer
4
and a polysilicon gate structure
5
(hereinafter “gate conductor” refers to both gate oxide layer
4
and a polysilicon gate structure
5
together). Oxide spacers
7
are formed along sidewalls of the gate oxide layer
4
and the gate structure
5
. Formed in the well region
3
between the gate structure
5
and the isolation regions
2
are source/drain region
6
into which impurities having a conductivity opposite to that of the impurities doped into the well region
3
, are shallowly doped.
Where a channel length, i.e., the spacing between the source and drain regions (item C of
FIG. 1
) of the above described MOS transistor is less than 2 &mgr;m, “short channel effects” such as punchthrough can occur. Punchthrough is associated with the merging of source and drain depletion layers, i.e., when the drain depletion layer extends across the substrate and reaches the source depletion layer, thereby causing a destructive conduction path or leakage current between the source and drain. A drain depletion layer forms and spreads as the voltage applied across the transistor from the drain to the source (hereinafter drain-source voltage V
DS
) is increased. At a certain drain-source voltage V
DS
called the punchthrough voltage, the width of the drain depletion layer approaches the channel length, and the depletion regions meet, resulting in punchthrough. Punchthrough results in, e.g., a constant drain current for increasing drain voltages.
Therefore, what is needed is a method and apparatus for controlling punchthrough in semiconductor devices.
SUMMARY
An embodiment of the present invention includes a MOS transistor that includes: a semiconductor substrate; a well region formed in the semiconductor substrate, where a trench region is defined in the well region; an isolator formed on a corner of the trench region, where the trench region is filled with polysilicon; a gate conductor formed over the trench region; and source/drain regions formed within the well region laterally aligned to the gate conductor.
An embodiment of the present invention includes a method of forming a MOS transistor, including the acts of: forming a well region in a semiconductor substrate; forming a trench region in the well region; forming an isolator in a corner of the trench region; filling the trench region with polysilicon; forming a gate conductor formed over the trench region; and forming source/drain regions within the well region on opposite sides of the gate conductor.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.
REFERENCES:
patent: 5453635 (1995-09-01), Hsu et al.
patent: 5472894 (1995-12-01), Hsu et al.
patent: 5972758 (1999-10-01), Liang
patent: 6020621 (2000-02-01), Wu
Anam Semiconductor Inc.
Goodwin David
Parsons James E.
Skjerven Morrill & MacPherson LLP
Wilczewski Mary
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