Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-12-11
1999-12-28
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438301, H01L 21336
Patent
active
060080973
ABSTRACT:
The present invention relates to a MOS transistor of semiconductor device and method of manufacturing the same and, in particular, to MOS a transistor of semiconductor device and method of manufacturing the same which can reduce asymmetry of drain current due to bias of drain current, facilitate shallow junction and reduce the area to a minimum by forming a source/drain.
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patent: 5705420 (1998-01-01), Ema
patent: 5904516 (1999-05-01), Park
Kimura, S., et al., Short-Channel-Effect-Suppressed Sub-0.1-.mu.m Grooved-Gate MOSFET's with W Gate., Jan. 1995, pp. 94-100.
Kinmura, S. et al., Short-Channel-Effect-Suppressed sub-0.1 -micrometer Grooved-Gate MOSFET's with W Gate., pp. 94-100, Jan. 1995.
Baek Kyu Ha
Nam Kee Soo
Yoon Yong Sun
Electronics and Telecommunications Research Institute
Lindsay Jr. Walter L.
Niebling John F.
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