Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-08-25
2003-07-29
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S344000, C257S340000, C257S022000, C257S027000, C257S336000, C257S327000
Reexamination Certificate
active
06600200
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a MOS transistor, a method for fabricating a MOS transistor and a method for fabricating two complementary MOS transistors.
During the development of short-channel MOS transistors, measures have to be taken to suppress short-channel effects such as VT rolloff, drain induced barrier lowering or punch-through effects and at the same time to ensure a sufficiently high threshold voltage for the transistors having a gate dielectric thickness that decreases with channel length.
It has been proposed (for example in the following papers: Proc. ESSDERC 1996, pp. 505-514, by T. Skotnicki; IEDM Tech. Digest 1993, pp. 433-436, by T. Ohguro et al.; and Proc. ESSDERC 1996, pp. 321-324, by L. Risch et al.), for the purpose of improving DC parameters, in particular charge carrier mobility in the channel region, in the case of short-channel transistors on conventional semiconductor substrates, to reduce a contribution of a vertical electric field in the channel region. The vertical effective field in the channel region greatly determines the charge carrier mobility. Reducing the vertical field necessitates reducing the dopant concentration in the channel region. However, that in turn increases the influence of the transverse drain field and leads to undesirable short-channel effects.
To that end, it has been proposed to realize the MOS transistor on a relatively highly doped semiconductor substrate with a dopant concentration of about 10
18
cm
−3
and to provide a 20 to 50 nm thin undoped epitaxial layer in the channel region. In that case, care must be taken in the fabrication process to ensure that the relatively high doping does not diffuse out from the semiconductor substrate into the channel region. The source/drain regions project right into the highly doped substrate. Since the influence of the dopant concentration in the channel region on the threshold voltage decreases greatly with the distance from the gate dielectric, an adequate threshold voltage cannot be achieved in the case of that proposal with polysilicon as gate electrode material. The use of new gate materials, for example SiGe, is therefore necessary.
A further disadvantage of that proposal is that steep dopant gradients do not concomitantly scale to a sufficient extent when the size of the structure is reduced further. As a result, the increase in the current in the on state of the transistor becomes smaller and smaller.
As an alternative, it has been proposed to realize short-channel MOS transistors in SOI substrates, which have an insulating layer and a monocrystalline silicon layer on a support wafer. The active regions of those transistors are realized in the monocrystalline silicon layer. The capacitances of the source/drain regions with respect to the substrate are thereby reduced. One disadvantage of that alternative is in the high price of the SOI substrates and the high defect density in the monocrystalline silicon layer of SOI substrates.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a MOS transistor, a method for fabricating a MOS transistor and a method for fabricating two complementary MOS transistors, which overcome the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provide a MOS transistor that can be realized as a short-channel MOS transistor with improved CMOS gate transit times and an improved output current.
With the foregoing and other objects in view there is provided, in accordance with the invention, a MOS transistor, comprising a semiconductor substrate; a well doped by a first conductivity type in the semiconductor substrate, the doped well having a surface; an epitaxial layer having a dopant concentration of less than 10
17
cm
−3
and a given thickness, the epitaxial layer disposed on the surface of the doped well; source/drain regions doped by a second conductivity type opposite to the first conductivity type, the source/drain regions disposed in the epitaxial layer, and the source/drain regions having a depth less than or equal to the given thickness; and a channel region disposed in the epitaxial layer.
With the objects of the invention in view, there is also provided a method for fabricating a MOS transistor, which comprises producing a well doped by a first conductivity type in a semiconductor substrate; growing an epitaxial layer with a given thickness and a dopant concentration of less than 10
17
cm
−3
on a surface of the doped well; producing a gate dielectric on a surface of the epitaxial layer; producing a gate electrode on a surface of the gate dielectric; and producing source/drain regions doped by a second conductivity type opposite to the first conductivity type with a depth less than or equal to the given thickness, in the epitaxial layer.
The term “depth” is used herein to designate an extent perpendicular to the surface of the epitaxial layer, measured from the surface of the epitaxial layer.
Since the source/drain regions are disposed in the weakly doped epitaxial layer in the MOS transistor, the capacitance of the source/drain regions is considerably reduced. Therefore, the MOS transistor exhibits improved gate transit times and an improved output current at a driving voltage of 0 volts. When the substrate is connected up in a comparable manner, the MOS transistor is comparable, with regard to speed, with a MOS transistor which is realized in the monocrystalline silicon layer of an SOI substrate.
In particular, a monocrystalline silicon wafer is suitable as the semiconductor substrate.
In accordance with another feature of the invention, in order to fabricate a MOS transistor with a channel length of less than 130 nm, it is advantageous to choose the thickness of the epitaxial layer to be between 100 and 200 nm.
In accordance with a further feature of the invention, a doped layer having a depth which is smaller than the depth of the source/drain regions, having a thickness which is smaller than the thickness of the epitaxial layer and which is doped by the first conductivity type, that is to say by the same conductivity type as the doped well, is disposed in the epitaxial layer between the source/drain regions. The threshold voltage of the MOS transistor is set by the provision of the doped layer. In this way, a sufficiently high threshold voltage can be obtained even with a very thin gate dielectric.
The term “depth” of the source/drain regions is used herein to designate the distance between the surface of the epitaxial layer and the interface between the source/drain regions and the semiconductor material of the epitaxial layer, perpendicular to the surface of the epitaxial layer.
In accordance with an added feature of the invention, the doped layer is disposed at a depth of between 10 and 50 nm. It preferably has a thickness of between 10 and 50 nm. The dopant concentration is preferably between 5×10
17
and 5×10
18
cm
−3
. The thickness of the gate dielectric is preferably between 2 and 4 nm.
In accordance with an additional feature of the invention, with regard to suppressing punch-through effects, it is advantageous for a further layer doped by the first conductivity type to be disposed underneath the first-mentioned doped layer. In this case, the further doped layer may be disposed not only in the epitaxial layer but also at the interface between the highly doped well and the epitaxial layer.
In accordance with yet another feature of the invention, the further doped layer is disposed at a depth of between 50 and 200 nm and has a thickness of between 10 and 50 nm. The dopant concentration in the further doped layer is preferably 10
17
to 5×10
18
cm
−3
.
In order to fabricate the MOS transistor, firstly the well doped by the first conductivity type is produced in the semiconductor substrate. The epitaxial layer is grown on the surface of the doped well. The epitaxial layer is preferably grown undoped. The grown epitaxial layer is actually weakly
Lustig Bernhard
Risch Lothar
Schäfer Herbert
Greenberg Laurence A.
Infineon - Technologies AG
Lee Eddie
Locher Ralph E.
Nguyen Joseph
LandOfFree
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