Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-19
2001-08-28
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S265000, C438S594000
Reexamination Certificate
active
06281079
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates in general to the field of semiconductors, and specifically to a MOS transistor used as a selection transistor in a single-transistor memory cell, and to a production process.
MOS transistors form the basis of a large number of integrated circuits such as memory circuits or logic circuits. The growth in the integration density of integrated circuits requires that the gate length of the transistors be continually reduced. The gate length is the distance between the conductive regions of the MOS transistor, namely, the source and the drain. It is known in the prior art to provide the gate with nitride encapsulation. In particular, it is known to form the customary insulating spacers on the gate side walls from nitride in order to minimize the spacer thickness without detrimentally influencing the insulating effect. It is known that nitride spacers or a nitride etching stop layer on a top and a side gate insulation made of oxide, for example, can be used to produce a self-aligned contact with the source and the drain, in which the top and side gate insulation is not etched or attacked, or is etched or attacked only minimally.
The reduction in the gate length leads to increasing field strengths and hence to problems, particularly with the breakdown voltage and reliability of the transistor because of leakage currents.
Such a transistor having nitride encapsulation can be used, by way of example, as a selection transistor in a DRAM memory cell. There are a multiplicity of cell designs for DRAM memories. One example is a so-called trench cell with a surface strap. In this cell design, the storage capacitor is produced in a trench in the semiconductor substrate, and the storage electrode is configured in the trench. The capacitor dielectric covers the trench wall. The selection transistor is configured adjacent the trench. The electrical connection between the storage electrode and a doped region of the selection transistor is produced with a polysilicon structure (surface strap) that is configured on the substrate surface and overlaps the trench filler and the doped region.
With single-transistor memory cells, particularly DRAM memory cells, a leakage current results, in particular a current caused by the so-called GIDL effect (GIDL =Gate Induced Drain Leakage). A GIDL current causes the information retention time of the cell to be reduced. This applies particularly to the side of the selection transistor connected to the storage capacitor. Therefore, the GIDL current needs to be minimized.
One measure for reducing the GIDL effect is to reduce the diffusion of ion implantations below the gate. This is done by reducing the high-temperature steps after the critical implantations (implantation of source and drain). The associated additional process limitations are a considerable disadvantage. Another possibility is a complex, complete redesign of the module. However, both measures have limited effectiveness.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a MOS transistor in a single-transistor memory cell having an insulating spacer acting as an oxidation barrier, in which the GIDL effect is effectively minimized, as well as a production process for such a MOS transistor.
With the foregoing and other objects in view there is provided, in accordance with the invention, a MOS transistor in a single-transistor memory cell, comprising:
a semiconductor substrate having a substrate surface, a first conductive region and a second conductive region;
a gate oxide disposed on the substrate surface;
a gate disposed on the gate oxide over an area between the first conductive region and the second conductive region; and
an insulating spacer disposed on the side wall of the gate, the spacer acting as an oxidation barrier;
the gate oxide insulating the gate from the semiconductor substrate and having a thickened area in a region below the side wall of the gate.
In accordance with an added feature of the invention, the insulating spacer is a silicon nitride spacer.
In accordance with an additional feature of the invention the gate includes a layer selected from the group consisting of a tungsten silicide layer and a polysilicon layer.
In accordance with another feature of the invention, the gate includes a tungsten silicide layer and a polysilicon layer.
In accordance with a further added feature of the invention, the gate includes a layer selected from the group consisting of a tungsten silicide layer and a polysilicon layer.
In accordance with a further additional feature of the invention, the gate includes a tungsten silicide layer and a polysilicon layer.
In accordance with yet another feature of the invention, the MOS transistor is a selection transistor in a DRAM memory cell.
With the objects of the invention in view, there is also provided a process for producing an MOS transistor in a semiconductor substrate which comprises:
producing a gate oxide on a semiconductor substrate;
producing a gate on the gate oxide, and producing the gate with a side wall;
forming a thickened area of the gate oxide below the side wall of the gate by performing an oxidation step;
subsequently, creating an oxidation barrier by forming an insulating spacer on the side wall of the gate; and
producing doped regions adjacent the gate.
In accordance with an added mode of the invention, the oxidation step is performed at a temperature from 700° C. to 900° C.
In accordance with an additional mode of the invention, the oxidation step is a wet oxidation step.
In accordance with another mode of the invention, the oxidation step is performed at a temperature from 700° C. to 900° C., and is performed as a wet oxidation.
In accordance with a further added mode of the invention, after performing the oxidation step, LDD implantation is performed.
In accordance with a further additional mode of the invention, before performing the oxidation step, a passivation step to passivate the side wall of the gate is performed.
In accordance with yet an added mode of the invention, before performing the oxidation step, a passivation step at a high temperature is performed.
In accordance with yet an additional mode of the invention, before performing the oxidation step, a passivation step at a temperature from 1000° C. to 1150° C. is performed.
In accordance with yet another mode of the invention, the gate is produced with a tungsten silicide layer.
The use of a bird's beak in a MOS transistor for reducing the hot-electron effect is disclosed, for example, in U.S. Pat. No. 5,306,655. The transistors described there are insulated at the side by oxide spacers.
The invention is based on providing a thickened area in the gate oxide in the region below a side wall of the gate, i.e. a so-called bird's beak, in a MOS transistor in a single-transistor memory cell having an insulating spacer acting as an oxidation barrier. The production process enables the thickened area of the gate oxide to be produced before the insulating spacers are produced. After the gate has been etched, an oxidation step is performed which produces a thickened area in the gate oxide below the side wall of the gate. After this, an insulating spacer is produced on the side wall of the gate. The spacer is made of nitride or another material acting as an oxidation barrier. Finally, the MOS transistor is finished using known methods (particularly by implantation of the doped regions).
The lateral oxidation component necessary for forming the bird's beak is produced by selecting suitable process conditions. For example a relatively low oxidation temperature in the range from 700 to 900° C. is used, with a preferred temperature of around 800° C. Wet oxidation can additionally or alternatively be used by adding hydrogen or a hydrogen compound for at least part of the oxidation step.
In order to prevent undersirable excessive oxidation of the gate tracks themselves, it is advantageous, depending on the material of the gate, to passivate the exposed s
Heineck Lars-Peter
Schweeger Giorgio
Chaudhuri Olik
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Pham Haoi
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