Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-31
2002-06-04
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C365S185330
Reexamination Certificate
active
06399987
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a MOS transistor employed in a memory cell and a method of fabricating the same.
2. Description of the Related Art
A MOS transistor, one of the basic components in a semiconductor integrated circuit, is generally formed in an N-type or P-type well. Here, with the exception of special cases, a drain voltage Vdd is applied to the N wells, and a source voltage Vss is applied to the P wells. When a plurality of NMOS transistors are included in a single P well, only a single common contact is formed for applying well bias to the plurality of NMOS transistors, in order to reduce the chip area, instead of forming a plurality of contacts for individual NMOS transistors. When a single, common contact-type bias contact is used, a problem such as a “latch-up” phenomenon may occur in NMOS transistors located relatively far away from the well bias contact due to resistance, which increases in proportion to the distance between an NMOS transistor and its contact. The latch-up is a phenomenon that occurs when a MOS transistor is abnormally turned on due to a change in external voltage, electrical noise or ion radiation, thereby abnormally changing the electrical characteristics of the transistor or damaging the transistor.
Individual formation of well bias contacts for each of a plurality of NMOS transistors is preferred to prevent the latch-up phenomenon, but this tends to increase the size of a chip. Achieving good electrical characteristics conflicts with reducing the size of a chip, and it is not desirable to sacrifice either aspect. For a compromise between improvement of electrical characteristics and reduction of a chip size, a method of forming a well bias contact for every pair of two transistors has been proposed.
FIG. 1
is a sectional view for illustrating a well bias area region of a typical MOS transistor. Referring to
FIG. 1
, two gate patterns, each of which includes a gate oxide film
12
, a gate electrode
14
, a capping layer
16
and a gate spacer
18
, are formed on a semiconductor substrate
10
having a P-well of a first conductivity type. N-type impurity regions referred to as source/drain regions
26
, of a second conductivity type are formed around each gate pattern on the semiconductor substrate
10
. Reference numeral
20
denotes an interlayer insulating film, and reference numeral
22
denotes a contact for the source/drain region
26
. Reference numeral
24
denotes a well bias area which is formed by ion-implantation of impurities of the first conductivity type into the semiconductor substrate
10
.
Reference numeral
22
denotes a contact to which voltage Vdd for a transistor is applied. Reference numeral
22
′ serves as both a contact for the application of voltage Vss and a contact for the application of well bias voltage.
There is a limitation as to how much the area of a contact for applying well bias to typical NMOS transistors in a semiconductor substrate can be reduced, since the reduction may deteriorate the electrical characteristics of a MOS transistor. Accordingly, there is a limitation in improving the integrity of a semiconductor device by reducing the contact area for a MOS transistor.
SUMMARY OF THE INVENTION
To address the above limitations, it is a first object of the present invention to provide a MOS transistor having a self-aligned well bias area, in which higher integrity can be achieved by reducing the chip area while its electrical characteristics are sustained without causing a latch-up phenomenon.
It is a second object of the present invention to provide a method of fabricating the MOS transistor having a self-aligned well bias area.
To achieve the first object of the invention, the present invention provides a MOS transistor having a self-aligned well bias area. The MOS transistor includes: a semiconductor substrate on which a well of a first conductivity type is formed; at least two gate patterns, each of which includes a gate oxide film, a gate electrode and a capping layer, which are sequentially stacked on the semiconductor substrate, and a gate spacer, which is formed on the sidewalls of the gate electrode and the capping layer; source/drain regions doped with second conductivity type impurities, the source/drain regions being formed in the surface of the semiconductor substrate adjacent to the gate patterns; a trench formed between the gate patterns by etching the semiconductor substrate in a manner of self-alignment using the gate spacer; a well bias area formed at the side of the lower portion and the bottom of the trench; and a contact filling the trench.
The capping layer is preferably an oxide film or a multiple film including an oxide film, and the contact is formed of tungsten (W).
Each of the source/drain regions is composed of an LDD region and a high concentration impurity region. The depth of the trench is formed to pass through the source/drain region and come in contact with the first conductivity type well of the semiconductor substrate. The butted contact is connected to the source/drain region at the side of the upper portion of the trench.
To achieve the second object of the invention, the present invention provides a method of fabricating a MOS transistor having a self-aligned well bias area. The method includes the following steps. A gate oxide film, a gate electrode and a capping layer are sequentially stacked on a semiconductor substrate with a first conductivity type well. Thereafter, the capping layer and the gate electrode are patterned, and ion-implantation is performed using the gate electrode as an ion-implantation mask, thereby forming LDD region. Subsequently, a gate spacer is formed. Second conductivity type impurities are ion-implanted in the semiconductor substrate using a gate pattern with the gate spacer as an ion-implantation mask, thereby forming a high concentration impurity region. A photoresist pattern is formed on the resultant structure such that the high concentration impurity region between gate patterns is exposed. Next, the semiconductor substrate is etched in a self-aligning manner using the photoresist pattern, thereby forming a trench deep enough to pass through the high concentration impurity region and to come in contact with the first conductivity type well. First conductivity type impurities are ion-implanted in the side of the lower portion and the bottom of the trench, thereby forming a well bias area. Finally, the photoresist pattern is removed and the trench is filled with conductive material, thereby forming a contact.
The capping layer is preferably formed of an oxide film or a multiple layer including an oxide film to a thickness of 2000-4000 Å, and its contact is formed of tungsten.
The above method may further include the step of forming an interlayer insulating film on the entire surface of the semiconductor substrate to cover the gate pattern after forming the high concentration impurity region.
A preferred depth of the trench from the surface of the semiconductor substrate is 0.2-0.8 &mgr;m, and the amount of ion-implantation for forming the well bias area is 1E13-1E15 ions/cm
2
.
The contact is formed by sufficiently depositing a conductive material on the semiconductor substrate and planarizing the surface of the resultant structure using a chemical mechanical polishing (CMP) process during which the capping layer is used as a polishing stopper.
According to the present invention, the contact is formed in the trench so that circuits having a high integration density can be obtained due to reduction of the area occupied by the circuit on a chip, without degradation of the electrical characteristics of the MOS transistors.
REFERENCES:
patent: 5568422 (1996-10-01), Fujiwara
Le Thao P
Mills & Onello LLP
Nelms David
Samsung Electronics Co,. Ltd.
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