Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-23
2002-12-17
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S591000, C438S240000, C438S585000, C257S410000, C257S324000
Reexamination Certificate
active
06495409
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to metal-oxide-silicon (MOS) transistors, and more particularly, to improved materials for use as gate structures of MOS transistors.
2. Description of the Related Art
MOS transistors have been a dominant technology in the silicon industry.
FIG. 1
illustrates a conventional MOS transistor
10
comprising a silicon substrate
12
, a source
14
, a drain
18
, and a gate
22
. The MOS transistor
10
further comprises a substrate electrode
26
, a source electrode
16
, a drain electrode
20
, and a gate electrode
24
formed on the substrate
12
, the source
14
, the drain
18
, and the gate
22
, respectively. Electrical connection to the substrate electrode
26
, the source electrode
16
, the drain electrode
20
, and the gate electrode
20
is via a substrate terminal B, a source terminal S, a drain terminal D, and a gate terminal G, respectively.
As is known to those skilled in the art, the silicon substrate
12
can be either p-type (as shown) or n-type, and the source
14
and drain
18
can be n
+
-type (as shown) or p
+
-type depending on the conductivity of the substrate
12
. As is also known to those skilled in the art, carriers enter the MOS transistor
10
through the source terminal S, leave through the drain terminal D, and are subject to the control of the action of signals applied to the gate electrode G. The voltage applied to the gate terminal G relative to ground is V
G
while the voltage applied to the drain electrode D relative to ground is V
D
. It should be understood that many variations of the foregoing structure are well know to those skilled in the art and the foregoing structure is meant to be illustrative and not limiting.
As shown in
FIG. 1
, the material used for the gate
22
is silicon dioxide (SiO
2
). There are certain disadvantages, however, associated with using such a gate material. In particular, in response to various market demands, the level of integration of MOS transistor based integrated circuit devices continues to increase. As a result, the size of MOS transistors in those devices decreases. In addition, in order to lower the power density consumed by the devices, the gate voltage V
G
is lowered accordingly. This leads to a need for thinner gate structures. It is contemplated that in order to meet future performance demands, conventional MOS transistors will be required to have gate thickness that are well below the tunneling limit of SiO
2
. MOS transistors incorporating such thin gate structures will suffer from excess leakage, which could result in device failure.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a gate dielectric material for an MOS transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
Additional features and advantages of the invention will be set forth in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the gate dielectric material particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described, the invention provides an MOS transistor comprising a substrate, a source, a drain, and a gate, wherein the gate comprises aluminum nitride.
To further achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described, the invention also provides a method of making an MOS transistor comprising forming a source and drain in a substrate, and forming a gate on the substrate, wherein the gate comprises aluminum nitride.
To still further achieve these and other advantages and in accordance with the purposes of the invention, as embodied and broadly described, the invention also provides a method of forming an aluminum nitride film on a silicon substrate comprising epitaxially growing aluminum nitride on the silicon substrate at a substrate temperature of about 600° C., and subsequently annealing the substrate and epitaxially grown aluminum nitride at a substrate temperature of about 950° C.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
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Sitar et al. “Growth Of AIN/GaN layered structures by gas source” J. Vac. Sci, Technology, pp. 316-322, Mar./Apr. 1990.*
S. Wolf, Silicon Processing for the VLSI Era, vol. 1—Process Technology. 1986.*
W. J. Meng et al., Growth of epitaxial aluminum nitride and aluminum nitride/ziconium nitride superlattice on Si(111), J. Vac Sci Technol. A 10(4), Jul./Aug. 1992.*
P. W. Wisk et al., Growth of GaN, AIN and InN by Electron Cyclotron Resonance Metal Organic Molecular Beam Epitaxy, Mat. Res. Soc. Symp. Proc. vol. 282 1993 Materials Research Socitey.
Manfra Michael J.
Pfeiffer Loren N.
West Kenneth W.
Wong Yiu-Huen
Agere Systems Inc.
Keshavan Belur
Smith Matthew
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