MOS transistor and method of manufacture

Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate

Reexamination Certificate

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C438S591000

Reexamination Certificate

active

07151059

ABSTRACT:
A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 μm or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.

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U. S. Appl. No. 09/597,012 filed on Jun. 20, 2000 entitled “MOS Transistor and Method of Manufacture” to Samir Chaudhry, et al. allowed on Dec. 10, 2003.

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