Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
2006-12-19
2006-12-19
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S591000
Reexamination Certificate
active
07151059
ABSTRACT:
A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 μm or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
REFERENCES:
patent: 4845047 (1989-07-01), Holloway et al.
patent: 4851370 (1989-07-01), Doklan et al.
patent: 5990516 (1999-11-01), Momose et al.
patent: 6025280 (2000-02-01), Brady et al.
patent: 6218276 (2001-04-01), Liu et al.
patent: 6221764 (2001-04-01), Inoue
patent: 6274915 (2001-08-01), Krishnan et al.
patent: 6288425 (2001-09-01), Adan
patent: 6551946 (2003-04-01), Chen et al.
patent: 6815295 (2004-11-01), Ueno et al.
patent: 0 758 715 (1997-04-01), None
patent: 1-204435 (1989-08-01), None
patent: 8288510 (1996-11-01), None
patent: 9045904 (1997-02-01), None
patent: 9283748 (1997-10-01), None
patent: 11026754 (1999-01-01), None
patent: 11097687 (1999-04-01), None
U. S. Appl. No. 09/597,012 filed on Jun. 20, 2000 entitled “MOS Transistor and Method of Manufacture” to Samir Chaudhry, et al. allowed on Dec. 10, 2003.
Chaudhry Samir
Chetlur Sundar Srinivasan
Gregor Richard William
Roy Pradip Kumar
Sen Sidhartha
Agere Systems Inc.
Pham Long
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