MOS transistor and fabrication method thereof

Details MOS transistor and fabrication method thereof MOS transistor and fabrication method thereof

2006-04-25

2006-04-25

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S408000

Reexamination Certificate

active

07033875

ABSTRACT:
A MOS transistor and a method for fabricating the MOS transistor. The present invention enables implementation of a stable semiconductor device that is capable of protecting against leakage current generation by improving the “LDD effect” and securing a large process margin by adjusting an “off” current. The method for fabricating a MOS transistor includes placing or arranging an epitaxial layer between a silicon wafer and a gate electrode, and forming three impurity regions, including a very low concentration impurity region, and a low concentration impurity region and a high concentration impurity region (source and drain region).

REFERENCES:
patent: 5627097 (1997-05-01), Venkatesan et al.
patent: 5817562 (1998-10-01), Chang et al.
patent: 5872039 (1999-02-01), Imai
patent: 6104063 (2000-08-01), Fulford et al.

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