Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-12-26
2003-02-18
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S298000, C257S300000, C257S301000, C257S330000, C438S242000, C438S243000, C438S206000, C438S253000
Reexamination Certificate
active
06521935
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a MOS transistor and a DRAM cell configuration having such a MOS transistor.
Presently, MOS transistors are usually realized using planar silicon technology, in which source, channel, and drain are disposed laterally. In such a case, the channel lengths that can be achieved are dependent on the resolution of the optical lithography used and on tolerances in the patterning and alignment.
MOS transistors are used, for example, in dynamic random access memory (DRAM) cell configurations. At the present time, use is made almost exclusively of a so-called one-transistor memory cell, including a MOS transistor and a capacitor, as the memory cell of a DRAM cell configuration. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor such that, when the transistor is driven through a word line, the charge of the capacitor can be read out through a bit line.
It is generally endeavored to produce a DRAM cell configuration that has a high packing density. To that end, it is advantageous to configure the MOS transistor as a vertical transistor, in which source, channel region, and drain are disposed one above the other. Such a MOS transistor can have a small space requirement independently of a channel length.
Such a MOS transistor is disclosed for example in L. Risch et al. “Vertical MOS Transistors with 70 nm Channel Lengths”, ESSDERC (1995), proceedings of the European Solid State Device Research Conference (ESS-DERC) Gil-Sur-Yette, France, pages 101 to 104. The lower source/drain region of the MOS transistor adjoins a surface of a substrate. Disposed on the lower source/drain region are a channel region and an upper source/drain region, which form a projection of the substrate. The projection is provided with a gate dielectric. A gate electrode of the MOS transistor laterally surrounds the projection. What is disadvantageous about such a MOS transistor is, in particular, the channel region that is insulated from the substrate and in which charge carriers can accumulate and alter the threshold voltage. Such a configuration leads to the so-called floating body effects.
U.S. Pat. No. 5,907,170 to Forbes et al. relates to a DRAM with an open bit line concept, a memory cell including a vertical selection transistor and a trench capacitor. The selection transistor is formed in a pillar that includes a layer sequence formed by lower source/drain region, body region, and upper source/drain region. A gate that controls the transistor is disposed on one side of the pillar. On the opposite side, a body contact is disposed on the body region. The body contact is connected to a body line. The gate is connected to a word line. The word line and the body line are routed separately through the entire cell array and are connected to a row decoder that drives the word line and the body line.
U.S. Pat. No. 5,559,368 to Chenming et al. discloses MOS field-effect transistors that are formed with a dynamic threshold voltage. For such a purpose, the body contact and the gate are electrically connected to one another so that very low threshold voltages can be realized. To implement the configuration, in the planar field effect transistor shown therein, contact holes are formed at the end of the channel width and realize an electrically conductive contact between the gate and the body region.
S. Assaderaghi et al., “Dynamic Threshold-Voltage MOSFET (DTMOS) for Ultra-Low Voltage VLSI”, IEEE Transactions on Electron Devices, Vol. 44, No. 3, (1997), 414, discloses a planar MOS transistor in which the channel region is electrically connected to the gate electrode of the MOS transistor. (As used here and below, channel region actually means the body of the MOS transistor, i.e., the semiconductor material that adjoins a source/drain region and the channel of the transistor and is doped by a conductivity type opposite to the conductivity type of the source/drain region. Thus, the channel itself is not electrically connected to the gate electrode.) The connection results in a variable threshold voltage of a transistor. In general, the threshold voltage of a transistor depends on the voltage difference between a source/drain region and the channel region. If the MOS transistor disclosed is not driven, which, as a rule, means that 0 volts is present at the gate electrode and, due to the connection, also at the channel region, then the voltage difference between the source/drain region and the channel region is greater than if the MOS transistor is driven, which means that the operating voltage is present at the gate electrode and, hence, the channel region. Consequently, the threshold voltage of the MOS transistor is larger in the event of non-driving than in the event of driving. The large threshold voltage in the event of non-driving of the MOS transistor brings about particularly small leakage currents. The small threshold voltage in the event of driving of the MOS transistor makes it possible to use a low operating voltage.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a MOS transistor and method for fabricating it, and DRAM Cell configuration and method for fabricating it that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that provides a MOS transistor configured as a vertical transistor and in which floating body effects are avoided. The invention provides a method for fabricating such a MOS transistor. The invention also provides a DRAM cell configuration in which such a MOS transistor is used, and also a method for fabricating such a DRAM cell configuration.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a MOS transistor including a substrate, an upper source/drain region, a body region, a lower source/drain region, the upper source/drain region, the body region, and the lower source/drain region stacked as layers one above another and forming a projection of the substrate, the projection having a first lateral area and a second lateral area disposed opposite the first lateral area with respect to the projection, a gate dielectric adjoining the first lateral area, a gate electrode adjoining the gate dielectric, a patterned conductive structure adjoining the second lateral area at a portion of the body region and adjoining the gate electrode, and the conductive structure forming a conductive connection between the body region and the gate electrode.
Because the channel region is electrically connected to the gate electrode through the conductive structure, charge carriers generated in the channel region can flow away. Floating body effects are thereby avoided.
The MOS transistor additionally has a variable threshold voltage, which is likewise attributable to the connection of the channel region to the gate electrode. If the MOS transistor is not driven, a voltage difference between the channel region and one of the source/drain regions is particularly high so that the MOS transistor has a particularly high threshold voltage, which leads to fewer leakage currents. If the MOS transistor is driven, then a voltage difference between the channel region and the source/drain region is smaller so that the MOS transistor has a smaller threshold voltage and can be operated with a small operating voltage.
The projection may have, for example, a quadrangular horizontal cross-section, that is to say, a cross-section parallel to a surface of the substrate. The cross-section may be, for example, rectangular or square. However, the horizontal cross-section may also assume any other form. For example, the horizontal cross-section can be an ellipse or a circle. In such a case, the first lateral area and the second lateral area merge with one another without any edges.
If the horizontal crossed section of the projection is quadrangular, then the first lateral area of the projection is preferably opposite the second lateral are
Krautschneider Wolfgang
Schlösser Till
Willer Josef
Greenberg Laurence A.
Huynh Andy
Infineon - Technologies AG
Locher Ralph E.
Nelms David
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