Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-21
2001-05-08
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S151000, C438S156000, C438S273000
Reexamination Certificate
active
06228719
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOS-gated power device with low output resistance and low capacitance, and to a related manufacturing process. MOS-gated power devices include, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices.
2. Discussion of the Related Art
A primary goal of the designers of MOS-gated power devices is to reduce, as far as possible, the output resistance (or “on” resistance) and the various capacitances associated with the power device structure.
These parameters can be reduced by increasing the integration density of the elementary functional units (polygonal cells or stripes), which constitute a MOS-gated power device, by exploiting photolitographic techniques and manufacturing processes more and more similar to those used in Very Large Scale of Integration (VLSI) technologies.
However, the physical structure of the MOS-gated power devices limits the degree to which the integration density can be increased. These limits can be better understood considering the distinct components of the on resistance of a MOS-gated power device, which are: the channel resistance Rc, which is the component associated with the channel region of the MOS-gated power device; the accumulation region resistance Racc, which is the component associated with the surface region of those portions of the common drain layer (i.e. the lightly doped epitaxial layer wherein the elementary functional units are formed) disposed between the body regions of the elementary functional units; the JFET resistance Fjfet, which is the component associated with those portions of the common drain layer disposed between the depletion regions of the body regions of the elementary functional units; and the epitaxial layer resistance Repi, which is the component associated with those portions of the common drain layer beneath the body regions of the elementary functional units.
The channel resistance Rc and the accumulation region resistance Racc (both associated with regions near the surface of the common drain layer) can be reduced by scaling down the dimensions of the elementary functional units and by employing photolithographic machines with better optical resolution. Differently, the JFET resistance Rjfet and the epitaxial layer resistance Repi can be reduced only modifying the physical structure of the MOS-gated power devices. In fact, reducing the distance between the elementary functional units (cells or stripes), causes the Fjfet component to significantly increase, the increase being more pronounced the higher the resistivity of the common drain layer.
This means that in order to prevent the on resistance from significantly increasing, the minimum distance to which the elementary functional units of the MOS-gated power device must be kept increases with the increase of the resistivity of the common drain layer. By way of example, in devices designed to operated in a voltage range of approximately 60 V, the distance between the elementary functional units can be between 4 &mgr;m and 10 &mgr;m, while in the case of devices designed to operate in higher voltages of about 500 V, wherein the common drain layer is resistive, the distance between 15 &mgr;m and 20 &mgr;m.
Therefore, if in the attempt to increase the integration density it is desired to reduce the distance between the elementary functional units (cells or stripes), so that the gate-drain (or feedback) capacitance can be reduced, without however increasing the output resistance of the MOS-gated power device, it is necessary to increase the doping concentration of the common drain layer. This however reduces the breakdown voltage of the MOS-gated power device.
One known technique to overcome this drawback is described in the U.S. Pat. No. 4,376,286: the doping concentration in the portions of the common drain layer between the elementary functional units is increased by means of an implant of N type dopants, without affecting the doping concentration of the common drain layer beneath the body regions of the elementary functional units. In this way, it is possible to reduce the distance between the elementary functional units (and consequently reducing the feedback capacitance of the MOS-gated power device), without increasing the Fjfet component of the on resistance.
One of the limitations of this technique is that only the JFET component of the on resistance can be reduced, but not the epitaxial layer resistance Repi. Furthermore, an additional mask may be required in the manufacturing process, to prevent the N type dopants from being implanted at the edge of the power MOS device chip.
In view of the state of the art described, it is an object of the present invention to provide a MOS-gated power device with a low output resistance and low capacitance, without negatively affecting the breakdown voltage.
SUMMARY OF THE INVENTION
According to the present invention, this and other objects are achieved in a MOS-gated power device comprising a plurality of elementary functional units, each elementary functional unit comprising a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value, wherein a respective lightly doped region of a second conductivity type is respectively disposed under each body region, each respective lightly doped region having a second resistivity value higher than said first resistivity value.
As a result of the present invention, and specifically due to the presence of the lightly doped regions under the body regions of the elementary functional units, a MOS-gated power device is provided which, for a given breakdown voltage, has a common drain layer with a lower resistivity than that which would be necessary in a conventional MOS-gated power device with the same breakdown voltage. The reduced resistivity of the common drain layer not only provides a decrease of the JFET component Rjfet, but also of the epitaxial layer component Repi of the output resistance of the MOS-gated power device. Furthermore, it is possible to reduce the distance between the elementary functional units without increasing the JFET component, thus reducing the gate-drain capacitance of the MOS-gated power device.
The structure according to the present invention is particularly suitable for MOS-gated power devices of low voltages (30-200V), in which the dimension of the elementary functional units is comparable with the residual thickness of the epitaxial layer under the body regions.
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Ferla Giuseppe
Frisina Ferruccio
Rinaudo Salvatore
Galanthay Theodore E.
Morris James H.
Picardat Kevin M.
STMicroelectronics S.r.l.
Wolf, Greenfield & Sacks, P.
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