Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1995-06-21
1999-02-23
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438133, H01L 21336
Patent
active
058743383
ABSTRACT:
A MOS-technology power device including a semiconductor material layer of a first conductivity type having a body region disposed therein. The body region includes a heavily doped region of a second conductivity type, a lightly doped region of the second conductivity type and a heavily doped region of the first conductivity type and a process of making same. A method of making the semiconductor device includes forming an insulated gate layer on portions of the surface of the semiconductor material layer to leave selected portions of the semiconductor material layer exposed. Ions of the second conductivity type are implanted into the selected regions of the semiconductor material layer. The implanted ions are thermally diffused to form body regions, each body region including a heavily doped region substantially aligned with the edges of the insulated gate layer, and a lightly doped region formed by lateral diffusion of the first dopant under the insulated gate layer. Ions of the first conductivity type are then implanted into the heavily doped regions to form source regions substantially aligned with the edges of the insulated gate layer.
REFERENCES:
patent: 3319311 (1967-05-01), Mutter
patent: 3461360 (1969-08-01), Barson et al.
patent: 3764396 (1973-10-01), Tarui et al.
patent: 3821776 (1974-06-01), Hayashi et al.
patent: 3845495 (1974-10-01), Cauge et al.
patent: 3909320 (1975-09-01), Gauge et al.
patent: 3950777 (1976-04-01), Tarui et al.
patent: 3986903 (1976-10-01), Watrous, Jr.
patent: 4001860 (1977-01-01), Cauge et al.
patent: 4055884 (1977-11-01), Jambotkar
patent: 4142197 (1979-02-01), Dingwall
patent: 4145700 (1979-03-01), Jambotkar
patent: 4190850 (1980-02-01), Tihanvi et al.
patent: 4199774 (1980-04-01), Plummer
patent: 4233615 (1980-11-01), Takemoto et al.
patent: 4344081 (1982-08-01), Pao et al.
patent: 4345265 (1982-08-01), Blanchard
patent: 4376286 (1983-03-01), Lidow et al.
patent: 4399449 (1983-08-01), Herman et al.
patent: 4454523 (1984-06-01), Hill
patent: 4549193 (1985-10-01), Malhi et al.
patent: 4593302 (1986-06-01), Lidow et al.
patent: 4642666 (1987-02-01), Lidow et al.
patent: 4680853 (1987-07-01), Lidow et al.
patent: 4705759 (1987-11-01), Lidow et al.
patent: 4716126 (1987-12-01), Cogan
patent: 4794436 (1988-12-01), Blanchard
patent: 4798810 (1989-01-01), Blanchard et al.
patent: 4952992 (1990-08-01), Blanchard
patent: 4974059 (1990-11-01), Kiazer
patent: 5191396 (1993-03-01), Lidow et al.
patent: 5338961 (1994-08-01), Lidow et al.
patent: 5397728 (1995-03-01), Sasaki et al.
Wolf et al., "Silicon Processing for the VLSI Era vol. 1: Process Technology", pp. 303-308, 1986.
Proceedings of the IEEE, vol. 51, Sep. 1963, S.R. Hofstein, et al. "The Silicon Insulated-Gate Field-Effect Transistor", pp. 1190-1202.
IEEE Journal of Solid-State Circuits, vol. SC-10, No. 5, Oct. 1975, T.J. Rogers, et al., "An Experimental and Theoretical Analysis of Double-Diffused MOS Transistors", pp. 322-331.
Integrated Circuits Laboratory, Standford Electronics Laboratories, Standford University, Technical Report No. 4956-1, Mar., 1976, Michael D. Pocha, High Voltage Double Diffused Mos Transistors For Integrated Circuits, pp. 1-244.
IEEE Transactions on Electron Devices, vol. Ed-31, No. 1, Jan. 1984, J. G. Mena, et al., "Breakdown Voltage Design Considerations in VDMOS Structures", pp. 109-113.
Intel Corporation, Mountain View, University of California, Berkeley, John Wiley & Sons, A.S. Grove, "Physics and Technology of Semiconductor Devices", 1985, Month Unknown.
Patent Abstracts of Japan, JP-A-52 65943, Jan. 6, 1979 (Nippon Denki K.K.).
The Theory and Practice of Microelectronics, Chapters 4, 6, 7, 8, 10, 13 and 15, Ghandi, 1983, Month Unknown.
Ferla Giuseppe
Frisina Ferruccio
Booth Richard A.
Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
Niebling John F.
SGS--Thomson Microelectronics S.r.l.
LandOfFree
MOS-technology power device and process of making same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS-technology power device and process of making same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS-technology power device and process of making same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-306466