Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-06-16
2001-08-28
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S291000, C438S282000, C438S305000, C257S335000
Reexamination Certificate
active
06281062
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of semiconductor devices, and more specifically, to a metal oxide semiconductor field effect transistor (MOSFET) which exhibits excellent punchthrough characteristics, and which can be realized with a VLSI manufacturable process.
2. Discussion of Related Art
In order to fabricate future complex integrated circuits, the basic building block of the integrated circuits, the transistor, must become smaller. Smaller metal oxide semiconductor transistors (MOS) are formed by decreasing the channel length of the transistor. Future MOS transistors will have channel lengths of less than 0.5 &mgr;m. A problem with manufacturing such small channel devices is that the punchthrough voltage of these transistors decreases to an unacceptable level.
The punchthrough voltage of a device is the drain voltage which will cause the drain depletion region of the device to extend into the source depletion region. When this occurs the transistor conducts regardless of the gate voltage. This eliminates the ability of the transistor to act as a switch, i.e. to switch “on” and “off”. MOS transistors of less than 1 &mgr;m cannot be fabricated without adjusting to some degree the process recipe to raise the punchthrough voltage of the device.
Presently there are two techniques for adjusting the punchthrough voltage of short channel MOSFET transistors. The first technique, as shown in
FIG. 1
, employs a double-boron implant of a P type substrate to form an N channel enhancement mode MOSFET. The first boron implant, a threshold implant
12
, is a shallow implant of the channel region of the device. The threshold implant raises the threshold voltage of the transistor and prevents surface punchthrough. The second boron implant, the channel implant
14
, is a deeper implant of the entire channel region of the transistor. The channel implant prevents bulk punchthrough of the device.
The double-boron implant transistor is undesired because channel implant
14
adversely affects the performance characteristics of the transistor. The channel implant
14
is especially troublesome because it raises the doping at the depletion edge of the device, which affects the device's substrate sensitivity. Additionally, the channel implant adversely affects the sub-threshold slope (gate swing voltage) of the device and also affects threshold voltage.
The second punchthrough voltage adjusting technique is known as LATIPS, and is shown in FIG.
2
. The LATIPS transistor employs a large tilt-angle implanted punchthrough stopper (LATIPS). This implant forms higher concentration P type regions
16
under the gate to prevent bulk punchthrough. This implant is generated by tilting and rotating the wafer as the implant occurs. The LATIPS transistor also employs a threshold implant
18
to raise the threshold voltage and to prevent surface punchthrough.
The LATIPS transistor exhibits several undesirable features. First, the P implants
16
do not surround the entire drain. This requires wells to be deeper to prevent well punchthrough, leading to a reduction in packing densities. Second, the LATIPS technology has not been characterized extensively, making its successful use in the manufacturing environment questionable. This is because the rotational aspect of the punchthrough implant provides a doping uniformity which is dependant on the placement, shape, and layout of the fabricated transistor. Additionally, the LATIPS technique requires very specialized and expensive equipment which is difficult to obtain.
Thus, what is needed is a submicron transistor which exhibits excellent punchthrough characteristics without sacrificing other device performance characteristics and which can be fabricated with a VLSI manufacturable process.
SUMMARY OF THE INVENTION
The present invention is a lightly doped drain (LDD) submicron, highly reliable, VLSI manufacturable metal-oxide-semiconductor field effect transistor (MOSFET) which exhibits excellent punchthrough characteristics. A gate insulating layer is formed on a substrate of a first concentration of a first conductivity type. An inner gate electrode of a predetermined length and width is formed on the gate insulating layer. The inner gate electrode has laterally opposite sidewalls along the width of the inner gate electrode. First and Second punchthrough stop regions of a second concentration of the first concentration type are formed in the substrate in alignment with the laterally opposite sidewalls of the inner gate electrode. A pair of conductive spacers are formed adjacent to and in electrical contact with respective laterally opposite sidewalls of the inner gate electrode on the gate insulating layer. The conductive spacers are formed from either polysilicon, TiN, or some other conductive meterial and together with the inner gate electrode form the MOSFET gate electrode. A first source and a first drain of a first concentration of a second conductivity type are disposed in the first and the second punchthrough stop regions, respectively, self-aligned with the outer edges of the conductive spacers. Oxide spacers are formed adjacent to the outer edges of the conductive spacers. Second source and second drain regions of a second concentration of the second conductivity type are formed in the first source and the first drain regions, respectively, in alignment with the outside edges of the oxide spacers. Silicide is formed on the second source and second drain regions and on the inner gate electrode to decrease the contact resistance of the transistor. A threshold implant region of a third concentration of the first conductivity type is formed at the surface of the channel region of the transistor.
A goal of the present invention is to form a high speed, small channel transistor which exhibits excellent punchthrough characteristics.
Another goal of the present invention is to form a small channel transistor which is resistant to hot electron degradation.
Another goal of the present invention is to form a submicron transistor wherein punchthrough stop regions can be fabricated uniformly across a wafer and from wafer to wafer using standard processing equipment and techniques
Still yet another goal of the present invention is to form a transistor where the punchthrough stop regions are self-aligned beneath the gate of the transistor.
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Blakely , Sokoloff, Taylor & Zafman LLP
Chaudhuri Olik
Intel Corporation
Rao Shrinivas
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