MOS read-only semiconductor memory with selected source/drain re

Details MOS read-only semiconductor memory with selected source/drain re MOS read-only semiconductor memory with selected source/drain re

1995-03-27

1997-07-01

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257391, 257392, 365104, H01L 2976, H01L 2994, H01L 31062, H01L 31113

Patent

active

056441541

ABSTRACT:
Method and structure is disclosed for a read-only MOS semiconductor memory. An addressable array of a multiplicity of cells each comprising a single MOS transistor is coded for preselected cells by providing them with source/drain regions which are spaced apart from edges of their respective overlying gate electrode regions. This is accomplished by a masking step late in the fabrication sequence. In this way, a dense MOS memory having rapid manufacturing turn-around is provided.

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patent: 4837181 (1989-06-01), Galbiati et al.
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patent: 5291435 (1994-03-01), Yu
patent: 5313418 (1994-05-01), Wada et al.
patent: 5517061 (1996-05-01), Azmanov

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