MOS Random access memory cell with nonvolatile storage

Details MOS Random access memory cell with nonvolatile storage MOS Random access memory cell with nonvolatile storage

1982-12-29

1985-04-09

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Precharge

365189, G11C 1140

Patent

active

045105847

ABSTRACT:
A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit. If a positive charge state has been stored at the charge storage node (44) the transistor (42) is rendered conductive to pull the DATA node (22) to ground to restore the data state to the volatile memory circuit. If a negative charge state has been stored at the charge storage node (44) there is no load applied to either the DATA node (20) or the DATA node (22). The cross-couple transistors, (12,14) are fabricated to have different lengths such that the node (22) is driven to a high voltage state whenever a default condition is encountered, thereby restoring the original data state to the volatile memory circuit.

REFERENCES:
patent: 4475178 (1984-10-01), Kinoshita

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