Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-17
2001-09-04
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S234000
Reexamination Certificate
active
06284582
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits and to methods of manufacturing integrated circuits. More particularly, the present invention relates to a metal oxide semiconductor (MOS) controlled bipolar transistor and a method of manufacturing such a transistor.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs), such as, ultra-large scale integrated (ULSI) circuits, can include as many as one million transistors or more. The ULSI circuit can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). As the critical dimensions of ULSI circuits become smaller and smaller, transistor drive current is critical in determining overall integrated circuit speed and performance.
One of the factors that affects transistor drive current is the device architecture used in the transistor. In concurrent integration technology, CMOS FET (Complementary Metal-Oxide-Semiconductor Field-Effect Transistor) device architecture is typically considered to be dominant. CMOS FET architecture, however, has some limitations. First, the thickness of the gate dielectric is non-scalable. When the gate dielectric or gate oxide thickness is reduced to below 15Å, significant leakage current occurs due to a direct tunneling mechanism (i.e., charge carriers tunnel through the thin trapezoid potential barrier of gate oxide). The severe gate leakage current makes the MOS gate less capacitive but more resistive, therefore degrading the current drive due to a smaller amount of charge induced in the inversion channel. Second, MOSFETs are uni-polar devices. As such, only one type of carrier (either electron or hole) contributes to the channel conduction current, limiting the current drive capability.
In contrast, the Bipolar Junction transistor (BJT), used widely in the early stage of integrated circuit history, provides larger current drive capability due to its bipolar nature. That is, both types of charge carriers (i.e., electrons and holes) contribute to the current conduction. However, the BJT requires a relatively large amount of substrate area compared to MOSFETs. Accordingly, BJTs are not significantly utilized in ultra-large scale integration (ULSI) because of its large area consumption for a single device or transistor.
Thus, there is a need for a transistor architecture that combines the advantages of MOSFETs and BJTs, while attempting to avoid the disadvantages of both types of devices. Even further, there is a need for utilizing the direct tunneling leakage current through the ultra-thin gate dielectric as the base injection current for a lateral bipolar junction transistor built underneath the gate stack.
SUMMARY OF THE INVENTION
One embodiment relates to a method of forming a metal oxide semiconductor (MOS)-controlled bipolar transistor. The method includes tilt angle implanting a first impurity into a semiconductor substrate and implanting a second impurity into the semiconductor substrate to form an emitter and a collector.
Another embodiment relates to a transistor arranged as to combine the large current drive capacity of a bipolar junction transistor (BJT) with the smaller device size of a metal oxide semiconductor field effect transistor (MOSFET). The transistor includes a semiconductor structure, a gate located proximate the semiconductor structure, a gate insulator disposed intermediate the semiconductor structure and the gate, a source region located in the semiconductor structure, a drain region located in the semiconductor structure, and a buffer region located in the semiconductor structure proximate the drain region.
Another embodiment relates to a method of fabricating a transistor which combines the large current drive capacity of a bipolar junction transistor (BJT) with the smaller device size of a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a gate stack, large-tilt-angle implanting a first impurity in a semiconductor substrate, and implanting a second impurity to form a emitter and a collector.
Other principle features and advantages of the present invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.
REFERENCES:
patent: 5270227 (1993-12-01), Kamayama et al.
patent: 5342794 (1994-08-01), Wei
patent: 5728613 (1998-03-01), Hsu et al.
patent: 6043130 (2000-03-01), Gregory
patent: 6127236 (2000-10-01), Prall et al.
patent: 6214666 (2001-04-01), Mehta
Advanced Micro Devices , Inc.
Foley & Lardner
Nguyen Tuan H.
LandOfFree
MOS-gate tunneling-injection bipolar transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS-gate tunneling-injection bipolar transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS-gate tunneling-injection bipolar transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2543946