Modulating surface morphology of barrier layers

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

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438640, 438653, 438714, 438906, H01L 2128, H01L 21306

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059566086

ABSTRACT:
A process for fabricating electronic devices which includes the steps of providing a structure that includes a substrate with an overlying dielectric layer having one or more contact holes and/or vias formed therein; depositing a barrier layer over the structure so that the barrier layer penetrates into the contact holes and/or vias; plasma etching the deposited barrier layer so as to modify its surface morphology; and after modifying the surface morphology of the deposited barrier layer, depositing a metalization layer over the barrier layer. A two-step preclean to facet upper corners of the holes and/or vias and to clean bottoms of the holes and/or vias is performed prior to the deposition of the barrier layer.

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Park, et al., "Fabrication of 256Mbit Dram With a Fully Planarized Double Level Interconnection," VMIC Conference, pp. 45-51 (Jun. 27-29, 1995).

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