Modified poly-buffered locos forming technology avoiding the pos

Details Modified poly-buffered locos forming technology avoiding the pos Modified poly-buffered locos forming technology avoiding the pos

1996-05-07

1999-03-02

Fourson, George

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438453, 438439, 438448, H01L 2176

Patent

active

058770739

ABSTRACT:
A method for fabrication of modified poly-buffered LOCOS without positive charges trapping at the beak of the field oxide. The method employs DIW (Deionized Water) to be sprayed onto the wafer before gate electrode forming to eliminate the trapping of positive charges and reduce the undesired charge breakdown thereby increasing the yield of devices not containing this defect.

REFERENCES:
patent: H1041 (1992-04-01), Lux et al.
patent: 3706918 (1972-12-01), Barone et al.
patent: 4014772 (1977-03-01), Woods et al.
patent: 5506006 (1996-04-01), Chou et al.
patent: 5538917 (1996-07-01), Kunitou
patent: 5543343 (1996-08-01), Bryant et al.

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