Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2001-05-14
2004-07-13
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S706000, C438S710000, C438S712000, C438S723000, C216S067000
Reexamination Certificate
active
06762125
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor manufacture, and more particularly to facet etching useful for improving subsequent dielectric layer step coverage.
BACKGROUND OF THE INVENTION
A major goal of any dielectric deposition system is good step coverage. Step coverage refers to the ability of subsequent layers to evenly cover layers (“steps”) already present on the substrate. Facet etches are frequently used to provide superior step coverage. The standard facet etch uses a high energy argon ion which physically bombards the material being etched and thereby etches the oxide at an angle to allow subsequent material to have the best step coverage possible. However, if the argon ions etch through the oxide and reach metal or another conductor, they disperse their energy into the metal line or other conductor. This energy finds its way to a ground through a weak spot in the gate oxide thereby resulting in a blown gate.
In sputter etching, ions which impinge on horizontal surfaces have a minimal effect on etch rate and profile. However, the sputter yield of the etch at the comers is approximately four times that of the etch rate of a horizontal surface, thereby creating an extreme etch profile. The effect is the wearing away of the corners of a feature at approximately 45 degree angles. The material removed by the sputter etch is redeposited along the sides of the feature and along the surface of the substrate.
An issue associated with sputter etching is that some of the sputtered material redeposits frequently on the inside surfaces of the etching chamber. This redeposited material must be removed at intervals, thereby taking the etching chamber off-line.
SUMMARY OF THE INVENTION
The process of the present invention employs a two-step etching sequence wherein an insulating layer deposited on top of a plurality of conductive structures is first etched by a high energy inert gas ion to physically sputter the oxide material and form a faceted etch. The first step etch is terminated prior to reaching a predetermined target depth. The second step etch is conducted with a reactant gas to further remove the insulating material down to the target depth.
In a preferred embodiment, the method of the invention comprises forming a first layer comprising an insulating material superjacent a substrate comprising a plurality of conductive structures, at least some of the conductive structures being placed apart to form spaces between the conductive structures, such that the first layer forms in at least some of the spaces between the conductive structures and the first layer is formed to a thickness at least equal to the target depth. Next, the first layer is etched by directing a plasma of an inert gas at the first layer formed in at least some of the spaces between the conductive structures. The plasma is of sufficient energy to sputter material from the first layer thereby forming a facet etch in the first layer formed in the spaces between the conductive structures. The first etch is terminated when the first layer has been etched to a predetermined depth which is less than the target depth. Next, the first layer is etched, in a second etch, by contacting the first layer with a reactive chemical gas/plasma. The second etch is terminated when the first layer has been etched to the target depth.
Various other features, objects and advantages of the present invention will be made apparent from the following detailed description and the drawings.
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Bossler Mark A.
Kari Thomas S.
Polinsky William A.
Micro)n Technology, Inc.
Norton Nadine G.
Umez-Eronini Lynette T.
Whyte Hirschboeck Dudek SC
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