Misalignment tolerant techniques for dual damascene fabrication

Details Misalignment tolerant techniques for dual damascene fabrication Misalignment tolerant techniques for dual damascene fabrication

1998-07-10

2000-10-03

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438618, 438622, H01L 214763

Patent

active

061272639

ABSTRACT:
The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures are formed which compensate for misalignment between the via pattern and the trench pattern by widening the trench at the point where the misalignment has occurred. Methods and devices are also provided wherein the trench width is not affected by misalignment thus preventing electrical shorts between closely spaced interconnect lines, this technique results in a reduction of the width of the via. These dual damascene structures utilize two dielectric layers (210 and 216) having similar etching characteristics. Additionally, a hard mask layer (218) and an etch stop layer (214) having similar etching characteristics are used in these structures such that the etching characteristics of the dielectric layers are dissimilar to the etching characteristics of the hard mask and the etch stop layer. A trench (224) is formed in the hard mask layer (218). A photoresist (226) having a via pattern (228) is deposited on the hard mask layer (218) such that the via pattern (228) overlays the trench (224). The via pattern is anisotropically etched through any hard mask layer portion (230) which protrudes inside via pattern (228). This inventive technique results in widening the trench (222) while maintaining the original diameter of the via, even when the via and trench patterns are misaligned. In another embodiment the technique results in a trench (330) which is not widened, thus preventing electrical shorts which can result from misalignment between a via pattern (322) and a trench pattern (326). Etching degradation of etch stop and photoresist layers is reduced because the trench and the via hole are formed simultaneously. Further embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials (418) which form a hard mask upon exposure to radiation. In additional embodiments, manufacturing systems (610) are provided for fabricating IC structures. These systems include a controller (600) which is adapted for interacting with a plurality of fabrication stations (620, 622, 624, 626, 628, 630 and 632).

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U.S. application No. 09/017,350 filed Feb. 2, 1998 to Mehul B. Naik.

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