Misalignment test structure and method thereof

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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C438S017000, C438S021000

Reexamination Certificate

active

07015050

ABSTRACT:
A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.

REFERENCES:
patent: 6294909 (2001-09-01), Leedy
patent: 6790685 (2004-09-01), Lee
patent: 2003/0096436 (2003-05-01), Satya et al.
patent: 2003/0129509 (2003-07-01), Yamaguchi
patent: 2004/0124412 (2004-07-01), Huang et al.
patent: 2005/0176174 (2005-08-01), Leedy

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