Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-10-30
1998-11-10
Niebling, John
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438302, 438306, 438919, H01L 218238
Patent
active
058343474
ABSTRACT:
A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.
REFERENCES:
patent: 4908327 (1990-03-01), Chapman
patent: 4924277 (1990-05-01), Yamane et al.
patent: 4956311 (1990-09-01), Liou et al.
patent: 5036019 (1991-07-01), Yamane et al.
patent: 5216272 (1993-06-01), Kubokoya et al.
patent: 5334870 (1994-08-01), Katada et al.
patent: 5413945 (1995-05-01), Chien et al.
patent: 5492847 (1996-02-01), Kao et al.
Wolf et al., "Silicon Processing for the VLSI Era vol. 1: Process Technology", Latice Press, pp. 292-293, 1986.
Fukatsu Shigemitsu
Kubokoya Ryoichi
Ooya Nobuyuki
Shiratori Kenji
Booth Richard A.
Niebling John
Nippondenso Co. Ltd.
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