Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-30
2003-08-19
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S585000, C438S586000, C438S595000, C438S596000
Reexamination Certificate
active
06607950
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method for forming Metal Insulator Silicon transistors and devices obtained thereof. The metal gate and high-k dielectric are introduced using a replacement gate process.
STATE OF ART
High-k gate dielectrics and metal gate electrodes will be required in future CMOS technologies to maintain the performance gains with scaling. The problem of introducing both a new gate dielectric and electrode is unprecedented in conventional CMOS technology. The new materials must solve the electrical limitations of the SiO
2
/polysilicon gate stack that is still in use and they must be capable of being incorporated in a “CMOS” type of process flow. It is expected that for CMOS and CMOS related technologies having a gate length of 50 nanometer and below, such high-k gate dielectrics and metal gate will become a necessity. Because the new materials for the gate stack, comprising dielectric and electrode, are still under investigating in research projects world wide, a baseline process for transistor fabrication is required that allows research to be performed on different materials while minimising cross-contamination in the tools. The research will be done in an available standard CMOS production line or an R&D environment. If a conventional CMOS process sequence is used the gate stack is defined after definition and implantation of the active area regions and prior to the formation of the spacers and the junctions. In such sequence the front-end-of-line process tools might be exposed to the metal containing dielectric and gate. Therefore precautions have to be taken to avoid contamination due to the high-k dielectric and/or metal gate of the standard CMOS process tools. Such baseline process although initially intended for research, may later also be used in production environment.
In patent application EP0929105 a metal gate sub-micron MOS transistor and the method for making such a device is disclosed. This process sequence is straight forward, forming a gate stack comprising an oxide dielectric and a metal gate. This method consists of the steps of forming the standard gate stack but also including a nitride top layer, oxide spacer formation and Pre-Metal-Dielectric (PMD) formation. The PMD layer will be planarised using Chemical Mechanical Polishing (CMP) to expose the nitride layer on top of the gate stack. This nitride is removed by wet etch, while leaving the underlying polysilicon gate and gate oxide intact. Similar to the dual damascene technology used in back-end of line processing, via holes and trenches are defined in the PMD stack to be able to contact the source-drain regions and to form the metal wiring. Metal is deposited in these via holes, trenches and on top of the polysilicon gate. The metal will interact with the polysilicon during subsequent annealing steps converting the polysilicon gate into a silicide material, which acts as a metallic gate.
In U.S. Pat. No. 5,960,270 another method for forming a metal gate MOS transistor is disclosed. A polysilicon/silicon oxide gate stack is formed on a substrate, followed by the formation of the spacers and the junctions. A nitride layer is deposited overlying the semiconductor device and the substrate. On top of this nitride layer the inter-level dielectric (ILD) layer is formed. The ILD layer will be polished using the polysilicon layer as a polish stop, so having the top surface of polysilicon gate exposed. This polysilicon gate will be removed and replaced by a metal gate. Optionally the gate oxide is also replaced e.g. by a high-k dielectric layer.
SUMMARY OF THE INVENTION
One aspect of the invention is directed toward a replacement gate technology that provides a robust process flow to fabricate transistors with different high-k dielectrics and metal gates. The replacement gate process is an alternative process sequence that can be used to fabricate devices without any specialised processing tools, i.e. it can be executed in a standard CMOS production line and R&D environment, without contaminating the front-end-of-line tools. This replacement gate process also provides the advantage of performing the high thermal budget processes prior to deposition of the metal gate electrode. Such a process flow allows the investigation of the properties of high-k dielectrics and/or metal gates in a standard CMOS processing environment.
Another aspect of the present invention offers a replacement gate process sequence having good planarization properties.
Another aspect of the invention uses SiC as oxide and/or metal CMP stop layer, etch stop layer or spacer material.
Another aspect of the invention relates to the etching and removal of SiC using a dry etching process that can be performed in a standard process tool.
A method for forming a replacement gate structure comprising the steps of:
providing a semiconductor substrate;
forming a temporary stack wherein the top layer of said stack is made of a first material, said stack further comprising oxide and/or polysilicon;
forming spacers wherein said spacers are made of a second material, that can be etched selectively to said first material;
said first and said second material are selected from the group of SiC and nitride;
depositing a dielectric layer;
polishing said dielectric layer and exposing the top layer of said temporary stack;
removing the temporary stack and creating a cavity;
depositing in said cavity a high-k dielectric and a thin film, wherein said thin film is selected from the group of polysilicon or a metal;
depositing a tungsten layer; and
polishing said tungsten layer to expose the surface of said polished dielectric layer.
A method for forming a replacement gate structure comprising the steps of:
providing a semiconductor substrate;
forming a temporary stack wherein the top layer of said stack is made of a first material, said stack further comprising oxide and/or polysilicon;
forming spacers wherein said spacers are made of a second material, that can be etched selectively to said first material;
said first and said second material are selected from the group of SiC and nitride;
depositing a dielectric layer;
polishing said dielectric layer and exposing the top layer of said temporary stack;
depositing a layer of said first material;
patterning said layer of said first material above said temporary stack and removing said top layer of said temporary stack;
further removing the temporary stack and creating a cavity;
depositing in said cavity a high-k dieletric and a thin film, wherein said film consists of polysilicon or a metal;
depositing a tungsten layer; and
polishing said tungsten layer.
A method for forming a replacement gate structure comprising the steps of:
providing a semiconductor substrate;
forming a temporary stack wherein the top layer of said stack is made of a first material, said stack further comprising oxide and/or polysilicon;
forming spacers wherein said spacers are made of a second material, that can be etched selectively to said first material;
said first and said second material are selected from the group of SiC and nitride;
depositing a dielectric layer;
polishing said dielectric layer and exposing the top layer of said temporary stack;
removing the temporary stack and creating a cavity;
depositing in said cavity a high-k dielectric and a thick film, wherein said film is selected from the group of polysilicon or a metal;
patterning said thick film such that said cavity is overlapped.
A method for forming a replacement gate structure wherein said SiC layer is etched selectively to oxide, polysilicon or nitride using a dry etch process.
A method for forming a replacement gate structure wherein said high-k dielectric and/or said thin metal film are deposited by ALCVD.
In all following paragraphs “nm” means nanometer.
REFERENCES:
patent: 5960270 (1999-09-01), Misra et al.
patent: 6033963 (2000-03-01), Huang et al.
patent: 6054355 (2000-04-01), Inumiya et al.
patent: 6087231 (2000-07-01), Xiang et al.
patent: 6137126 (2000-10-01), Avanzino et al.
patent: 6143593 (2000-11-01), Augusto
patent: 617730
Badenes Goncal
Henson Kirklen
Rooyackers Rita
Vanhaelemeersch Serge
Interuniversitair Microelektronic Centrum (IMEC)
Knobbe Martens Olson & Bear LLP
Pham Long
LandOfFree
MIS transistors with a metal gate and high-k dielectric and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MIS transistors with a metal gate and high-k dielectric and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MIS transistors with a metal gate and high-k dielectric and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3125006