Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-06-28
2001-08-21
Ngô, Ngân V. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S288000
Reexamination Certificate
active
06278165
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a MIS transistor and a method for producing the same. More specifically, the invention relates to a MIS transistor having a large driving current and a small parasitic capacitance, and a method for producing the same.
As a request to achieve the scaling down of a transistor having the metal insulator semiconductor (MIS) structure grows more intense, the scaling down of the MIS transistor progresses steadily at present. The scaling down of the MIS transistor is carried out by using a technique called a scaling rule for forming a source/drain region in proportion to a gate length, specifically by reducing the junction depth of an impurity diffusion region, a so-called diffusion layer, which is to be a drain and/or source, as the gate length decreases when the gate length decreases.
However, in a fine transistor having a gate length of less than 0.2 &mgr;m, the depth (Xj) of diffusion is too small, so that there is a problem in that the resistance of the gate increase to increase the parasitic resistance of the whole transistor to reduce a substantial driving current. In order to reduce the parasitic resistance, it is possible that the depth of the junction is reduced when the metal silicidation of the source and drain to be introduced is carried out. However, when the reduction of the depth of the junction is too great, there is a problem in that the silicide metal does not remain in the diffusion layer and penetrates the substrate to cause the junction leak.
The problem in that the resistance increases or the silicidation is difficult to carry out when the junction is shallow has been solved by the art called an elevated source/drain, a concave transistor, a recessed channel transistor or the like. This transistor has a structure wherein the surfaces of the source and drain are higher than the channel surface of the transistor (e.g., S.M. Sze Physics of Semiconductor Devices second edition, 1981, pp490).
FIG. 1
shows a MIS transistor which has such a concave MOS structure and which comprises a semiconductor substrate
1
, source/drain regions
2
, a channel plane arranged therebetween, an SiO
2
film
51
provided on the top of the channel plane
7
, and a gate electrode
6
facing the channel plane via the SiO
2
, film
51
.
In
FIG. 1
, each or the source/drain regions
2
include a first impurity diffusion region
2
a
formed in the semiconductor substrate
1
(below the channel plane
7
in the drawing), and a second impurity diffusion region
2
b
laminated outside of the channel plane
7
(above the channel plane
7
in the drawing). Such a structure wherein the gate electrode
6
is surrounded by the second impurity diffusion regions
2
b
via the SiO
2
film
51
may be considered as a construction wherein a groove is formed in the source/drain regions
2
or as a construction wherein the second impurity diffusion regions
2
b
are elevated.
However, in the conventional MIS transistor having the structure shown in
FIG. 1
, the gate electrode
6
is surrounded by the source/drain diffusion layer
2
via the SiO
2
(insulator) film
51
, so that there is a problem in that the gate-to-drain capacitance and source-to-drain capacitance increase, so that the switching speed of the transistor deteriorates to a large extent.
As described above, in the conventional MIS transistor, there is a problem in that it is not possible to reduce both of the resistance of the source/drain diffusion layer and the gate parasitic capacitance.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a MIS transistor and a method for producing the same, capable of reducing both of the resistance of a source/drain diffusion layer and a gate parasitic capacitance.
In order to accomplish the aforementioned and other objects, according to a first aspect of the present invention, a MIS transistor basically comprises a semiconductor substrate, source/drain regions formed on the substrate, and a gate electrode provided above a channel region between the source/drain regions, the top surfaces of the source/drain regions formed on the semiconductor substrate being arranged toward the gate electrode from a reference plane of a channel plane in the semiconductor substrate, and the top surfaces of the source/drain regions are arranged toward the channel plane from a reference plane of an interface between a gate insulator film formed on the channel plane and the gate electrode.
In the MIS transistor according to the first aspect of the present invention, a groove may be formed in the top surface of the semiconductor substrate and has a bottom surface serving as the channel plane, the gate insulator film being formed in an opening of the groove via a protective film, the gate electrode being arranged on the top of the gate insulator film, the source/drain regions being arranged on both sides of the channel plane, so that a predetermined relationship between the top surfaces of the source/drain regions, the channel plane and the interface is established.
In addition, in the MIS transistor according to the first aspect of the present invention, the top surfaces of the source/drain regions laminated in places which sandwich the channel plane on the semiconductor substrate therebetween may be arranged toward the gate electrode from a reference plane of the channel plane, and the top surfaces of the source/drain regions may be arranged toward the channel plane from a reference plane of the interface between the gate insulator film formed on the channel plane via a protective film and the gate electrode.
Moreover, in the MIS transistor described in the above paragraph, the top surfaces of the source/drain regions provided so as to sandwich the channel plane therebetween may be elevated from the channel plane to be arranged on the side of the gate electrode, and the top surfaces of the source/drain regions may have a substantially flat surface having a level which is elevated and arranged on the side of the gate electrode, and an inclined surface which is inclined from the level of the flat surface to a level of the channel plane.
In addition, in the MIS transistor according to the first aspect of the present invention, the gate electrode surrounded by the gate insulator film provided on the upper side of the channel plane may have a cross section of a T shape, the lower side of which is tapered.
According to a second aspect of the present invention, a MIS transistor basically comprises a semiconductor substrate, source/drain regions formed on the substrate, and a gate electrode provided above a channel region between the source/drain regions, the top surfaces of the source/drain regions provided so as to sandwich the channel plane therebetween being elevated from the channel plane to be arranged on the side of the gate electrode, and the top surfaces of the source/drain regions having a substantially flat surface having a level which is elevated and arranged on the side of the gate electrode, and an inclined surface which is inclined from the level of the flat surface to a level of the channel plane, the gate electrode surrounded by the gate insulator film provided on the upper side of the channel plane having a cross section of a T shape, the lower side of which is tapered via a step portion.
According to a third aspect of the present invention, there is provided a method for producing a MIS transistor comprising a semiconductor substrate, source/drain regions formed on the substrate, and a gate electrode provided above a channel region between the source/drain regions, the method comprising the steps of: selectively forming an oxide film on the semiconductor substrate; using the selectively formed oxide film as a mask to carry out etching to form a groove; laminating a semiconductor layer in the groove to polish the top surfaces of the oxide film and the semiconductor film, and thereafter, removing the oxide film; using the semiconductor film as a mask to diffuse
Nishiyama Akira
Noguchi Mitsuhiro
Ono Mizuki
Oowaki Yukihito
Takashima Daisaburo
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Ngo Ngan V.
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