Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-09-09
2004-11-02
Hu, Shouxiang (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S270000
Reexamination Certificate
active
06812104
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a MIS semiconductor device and a method of fabricating the same, and more particularly to improvements of a source region and a drain region.
In order to meet a demand for a higher performance based on a higher integration density achieved by modern finer processing, when semiconductor integrated circuits (ICs) are fabricated, a gate electrode of a transistor is processed with a highest possible level of lithographic processing. Because of this, a variance occurs among gate electrodes and it leads to a variance in channel length and thus to a greater variance in transistor characteristics. Consequently, the product yield decreases. On the other hand, with miniaturization of semiconductor ICs, fine transistors and wiring are arranged very dense and the length of wiring increases. Even if the operation speed of transistors is to be increased based on the miniaturization, this cannot be achieved due to a parasitic capacitance and resistance between transistors and wiring.
FIG. 1
shows a structure of a conventional flat-type transistor. A gate electrode
3
is formed on a silicon substrate
1
, with a gate insulation film
2
interposed. Wiring elements
4
a
,
4
b
are formed on both sides of the gate electrode
3
, with an insulation film
9
interposed. A source diffusion layer
5
a
and a drain diffusion layer
5
b
are formed within the silicon substrate
1
. A region
6
between the diffusion layers
5
a
and
5
b
serves as a channel region. Numeral
7
denotes a device isolating insulation film, and numeral
8
an interlayer insulation film
8
.
Since the diffusion layers
5
a
and
5
b
are arranged adjacent to the channel region
6
within the silicon substrate
1
, this arrangement weakens a control power with which the gate electrode
3
controls the channel region
6
, and a so-called short-channel effect occurs. Consequently, the influence of a variation in lithographic processing increases.
For comparison with problems of a concave-type transistor and other conventional transistors, which will be described later,
FIG. 1
shows an electric current indicated by a dot-and-dash line in
FIG. 1
, which is produced when the flat-type transistor is operated. A current injected from the wiring element
4
a
enters the source diffusion layer
5
a
and then its accumulation layer (corresponding to a surface portion of the diffusion layer
5
a
, which is opposed to the gate electrode
3
with the gate insulation film
2
interposed, and having a carrier density several tens of times as high as the active impurity concentration in the diffusion layer). The current then flows into an inversion layer of the channel region
6
and into the wiring element
4
b
via an accumulation layer of the drain diffusion layer
5
b
and a diffusion region outside the accumulation layer. The current path is thus formed.
In the diffusion region outside the accumulation layer, a high-carrier-density region on the surface of the substrate
1
is lost, and the current flows deep into the diffusion layers
5
a
and
5
b
due to the carrier density determined by the active impurity concentration, and a so-called spreading resistance occurs. However, as indicated by a dot-and-dash line in
FIG. 1
, a substantially linear current path is formed.
Normally, the source and drain regions are formed such that impurities of a conductivity type opposite to the conductivity type of the substrate are ion-implanted, with the gate electrode used as a mask, and the impurities are activated or diffused by a heating process. The source region and drain region serve to connect the channel with the current paths to the wiring elements. In order to effect the connection with a sufficiently low resistance value, a deep region with high concentration needs to be formed by diffusion.
FIG. 2
shows a relationship between an electron concentration distribution and impurities in the drain diffusion region
5
b
at the time the flat-type transistor having a gate length of 0.1 &mgr;m is operated.
FIG. 2
shows, by device simulation, the area near the gate electrode
3
in FIG.
3
.
FIG. 2
shows only the area on the side of the drain diffusion layer
5
b
. In this simulation, 1V is applied to the gate electrode
3
, and 1V is applied to the drain diffusion layer
5
b.
A bias voltage applied to the source diffusion layer
5
a
is 0V. Thus, the current in the region near the source diffusion layer
5
a
is strongly influenced by the gate bias. In the vicinity of the drain diffusion layer
5
b
, the influence exerted on the surface of the substrate
1
by the gate electrode
3
is weaker than in the case of the source diffusion layer
5
a
, because of the bias voltage applied to the drain diffusion layer
5
b
. However, since the gate insulation film
2
is very thin, the current even near the drain diffusion layer
5
b
is strongly influenced by the gate electrode
3
. The following description is mainly directed to the drain diffusion layer
5
b
, but the relationship between the electron density/current density distribution and the position of the gate electrode
3
or the diffusion layer impurity distribution is basically applicable to the source diffusion layer
5
a.
The drain diffusion layer
5
b
extends to a location below or inside the gate electrode
3
to effect connection with the channel, thus forming a pn junction with channel impurities. The position of the pn junction is indicated by a bold line in FIG.
2
. At the position of the pn junction, impurities of opposite conductivity types cancel each other and the net impurity concentration becomes substantially zero.
Specifically, even if high-concentration impurities of about 1×20
20
cm
−3
are introduced in the drain diffusion layer
5
b
, as indicated by a broken line in
FIG. 2
, the impurity concentration in the vicinity of the edge of the gate electrode
3
generally decreases due to diffusion, and the impurity concentration in the region away from the edge near the center of the channel region further decreases toward the pn junction. A depletion layer forms near the junction, and the carrier concentration (electron density) is very low. Thus, the source diffusion layer
5
a
or drain diffusion layer
5
b
is electrically isolated from the substrate
1
of the opposite conductivity type. In
FIG. 2
, an electron density distribution curve represented by log
10
(electron density)=18 is away from the junction plate, compared to an impurity concentration distribution curve represented by log
10
(impurity concentration)=18. As is understood from this, the carrier density (electron density) is lower than the impurity concentration in the vicinity of the junction in the region of the drain diffusion layer
5
b
away from the surface of the substrate
1
.
When the transistor is operated, an inversion layer is formed in the surface portion of substrate
1
in the channel region
6
by the voltage applied to the gate electrode
3
. In
FIG. 2
, the region with high electron density at the surface portion of the channel region
6
is this inversion layer. On the other hand, an accumulation layer is formed in the drain diffusion layer
5
b
near the junction in the vicinity of the surface of the substrate
1
. This accumulation layer joins the inversion layer formed in the channel region
6
in the vicinity of the junction, thus forming a current path.
In
FIG. 2
, it is this accumulation layer where the electron density is higher than the impurity concentration in the drain diffusion layer near the junction plane in the vicinity of the surface of the substrate
1
. In the region of the drain diffusion layer
5
b
, which is away from the edge of the gate electrode
3
and has a high impurity concentration, the electron density is equal to the impurity concentration.
FIG. 3
shows a relationship between a current density distribution and the position of the gate electrode
3
or the impurity concentration distribution, when the same bias is applied to the same MOS tr
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Hu Shouxiang
Kabushiki Kaisha Toshiba
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