Minimizing resist poisoning in the manufacture of...

Details Minimizing resist poisoning in the manufacture of... Minimizing resist poisoning in the manufacture of...

2007-08-28

2007-08-28

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S672000, C257SE21577, C257SE21027

Reexamination Certificate

active

10993791

ABSTRACT:
The present invention provides a method for manufacturing an interconnect and a method for manufacturing an integrated circuit including the interconnect. The method of manufacturing an interconnect, among other steps, includes forming a via (160) in a substrate (130) and then forming a base getter material (210) in the via (160). The method further includes forming a photoresist layer (410) over the base getter material (210), the photoresist layer (410) having an opening (420) therein positioned over the via (160), and etching a trench (510) into the substrate (130) using the opening (420) in the photoresist layer (410).

REFERENCES:
patent: 6013579 (2000-01-01), Wang et al.
patent: 6103456 (2000-08-01), Többen et al.
patent: 6488509 (2002-12-01), Ho et al.
patent: 6489238 (2002-12-01), Tsui
patent: 6534397 (2003-03-01), Okada et al.
patent: 6586339 (2003-07-01), Plat et al.
patent: 6605536 (2003-08-01), Eissa et al.

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