Minimal recharge overhead circuit for domino SRAM structures

Details Minimal recharge overhead circuit for domino SRAM structures Minimal recharge overhead circuit for domino SRAM structures

1995-09-08

1997-03-25

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

36518905, 365194, G11C 700

Patent

active

056151608

ABSTRACT:
A system and method for improving a domino SRAM that eliminates the need for additional transistors in series with evaluation transistors. The regular structure inherent in RAM arrays is used to minimize both the effective recharge cycle time and the recharge power required to recharge the various levels of domino SRAM circuits. Using a clock signal as a reference, recharge signals are timed to each other and to other functional signals. By adjusting buffers and wiring delays associated with each recharge signal, the recharge signals sent to each level of logic are delayed until the recharge of the previous level is complete.

REFERENCES:
patent: 4851714 (1989-07-01), Hwang
patent: 4896057 (1990-01-01), Yang et al.
patent: 5068825 (1991-11-01), Mahant-Shetti et al.
patent: 5121003 (1992-06-01), Wiliams
patent: 5289431 (1994-02-01), Konishi
patent: 5481500 (1996-01-01), Reohr et al.
IBM Technical Disclosure Bulletin, vol. 37, No. 7, Jul. 1994; pp. 515-516.

Affiliated with

Also associated with

Rating

Minimal recharge overhead circuit for domino SRAM structures does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Minimal recharge overhead circuit for domino SRAM structures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimal recharge overhead circuit for domino SRAM structures will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2209641