Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
1998-11-02
2002-08-06
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257S787000, C438S113000, C438S124000, C438S126000, C438S127000, C438S458000, C438S460000
Reexamination Certificate
active
06429530
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package arrangement and, more particularly pertains to a light weight and miniaturized electronic package or module, wherein the dimensions between an integrated circuit comprising a semiconductor chip and those of a chip carrier have been optimized in order to provide for minimum weight and size relationships. Furthermore, the invention is directed to a novel method of forming the semiconductor package arrangement so as to produce a small, lightweight and essentially miniaturized chipsized chip carrier package module.
In the electronic packaging technology, particularly with regard to semiconductor chip configurations incorporating integrated circuits, considerable differences are encountered in connection with the extent of thermal expansion due to the different coefficients of thermal expansion which are encountered between semiconductor chips and the chip carrier substrate which supports the chips. This results in the carrier substrate, such as employed in a epoxy glass laminate plastic ball grid array (BGA) being subjected to high levels of generated mechanical stresses and to extensive warpage, tending to adversely influence the electrical interconnects and possibly resulting in the failure of the electronic circuitry. Moreover, the problem is excascerbated with the constant increases in the sizes of semiconductor chips and their overall dimensions, as is predicated on current industry projections or roadmaps and also past trends in the technology. For instances, current flip-chip ball grid array (BGA) package designs are frequently subject to serious reliability risk including chip fracture risks in view of high tensile stresses which are encountered in the semiconductor chip. In particular, these high stresses are generated at the backside of the chip and also along the edge of the chip, where wafer dicing induced damage frequently form sites for the initiation of cracks or propagation of fissures. In order to alleviate the foregoing problems, the invention is adapted to considerably reduce the magnitude of stresses which are encountered in the semiconductor or electronic circuitry package, and is, in particular, adapted to ameliorate any stresses which are encountered at the edge of the package to very low and tenable levels, thereby eliminating chip fracture risks which are based on thermally-induced stresses acting on the chip edge wherein fracture initiation is especially susceptible due to the dicing of the wafer. Moreover, there is a lessening of any risk of BGA solder ball fatigue being encountered by the balls which are located toward the edge of the so-called chip shadow, inasmuch as pursuant to the inventive electronic package arrangement, solder balls are no longer arranged at the edge of the chip shadow, thereby eliminating the generating of any stresses at that location. Basically, the present inventive concept of the electronic or semiconductor or chip package renders it possible to provide for molded packages where, currently, chip size limitations do not allow for molding; for example, such as for specialized types of flip-chip plastic ball grid array packages. The chip assembly is presently handled individually, irrespective as to whether by solder reflow or wirebond, and wherein the present inventive electronic or semiconductor chip package arrangement and the method of producing the foregoing simplifies to a considerable extent the assembly procedure to the wafer level, and with a considerable potential for reducing manufacturing and assembly processing costs.
DISCUSSION OF THE PRIOR ART
In the presently practiced technology which concerns itself with the producing of chip-package modules consisting of semiconductor chips which are supported on substrates, such as chip carriers, the above-mentioned problems are particularly in evidence with regard to high tensile stresses particularly along the edge of the chip generated due to warpage and differentials in coefficients of thermal expansion present between the semiconductor chip and the chip carrier, ordinarily due to the chip being of a size which is smaller than the overall size or peripheral dimensions of the chip carrier.
Nagano, U.S. Pat. Nos. 5,646,830 and 5,473,514 each disclose semiconductor devices having interconnecting circuit boards, wherein islands constituting semiconductor chip carriers are essentially sized so as to provide peripheral dimensions which are larger than those of the integrated circuits or semiconductor chips which are positioned thereon. The interconnections of these components; in effect, the semiconductor chips and the chip carriers are subjected to stresses generated proximate the edges thereof, and which result in potential interconnect failures due to warpage created by the differences in the coefficients of thermal expansion evident between the semiconductor chip and chip carrier components.
Miles, et al., U.S. Pat. No. 5,535,101 discloses a leadless integrated circuit package module including a substrate or semiconductor chip carrier having an integrated circuit chip mounted thereto. In that instance, the substrate or carrier is of a larger overall dimension than the semiconductor chip which, due to the differences in their coefficients of thermal expansion, will in response to the generation of heat again cause high tensile stresses to be generated due to warpage between the components, thereby potentially resulting in failure of the electrical interconnects or joints, especially along the edge regions intermediate the components.
Mullen, III, et al., U.S. Pat. No. 5,241,133 discloses a leadless pad array chip carrier having a semiconductor chip mounted thereon, wherein the carrier or substrate is of larger overall dimensions than those of the semiconductor chip. This structure, as in the previously described patents, will also lead to the generating of high stresses, particularly along the edges of the semiconductor chip, due to heat-induced warpage encountered during operation.
Tanaka, U.S. Pat. No. 5,363,277 discloses a semiconductor chip which is supported on a chip carrier, the latter of which possesses overall larger peripheral dimensions than the chip, and wherein the differing thermal expansion properties between the chip and the chip carrier substrate are conducive to the generating of high mechanical stresses and resultingly considerable warpage, thereby potentially resulting in fatigue and electrical connect joint failures.
SUMMARY OF THE INVENTION
Accordingly, in order to obviate the foregoing problems which are prevalent in the current state-of-the-technology, the present invention contemplates the provision of a semiconductor package arrangement or module, and also discloses a method for the forming of the package arrangement in which the size of the semiconductor chip is essentially larger than that of the chip carrier substrate. The chip carrier, which may be an organic laminate, multi-layer ceramic substrate or flexible substrate, as required by specific applications, is basically designed to possess overall smaller peripheral dimensions than those of the integrated circuit or semiconductor chip which is adapted to be mounted thereon. In essence, the chip carrier or substrate is electrically connected to the semiconductor chip through the intermediary of either solder bumps or a conductive adhesive, or other suitable flip chip connection methods. The utilization of an electronic package arrangement which comprises the mounting of a chip on a chip carrier or substrate, wherein the latter is of smaller peripheral dimensions than the semiconductor chip, and thereby eliminates in particular the edge stresses generated by the differentials in thermal expansion between the chip and chip carrier substrate, and in effect, reducing the previously generally encountered high mechanical stresses and extensive heat-induced warpage leading to potential failure of the electrical interconnects or solder joints.
Accordingly, it is an object of the present invention to provide a novel and
Chambliss Alonzo
Talbott David L.
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