Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-08-23
2003-11-04
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000, C438S250000, C438S393000
Reexamination Certificate
active
06642565
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a miniaturized capacitor with a solid-state dielectric (MIM or MIS capacitor), as can advantageously be used in particular for integrated semiconductor circuits and preferably for memories, for example dynamic random access memories (DRAMs). Capacitors of this type are known, for example, from U.S. Pat. No. 5,760,434, Published, British Patent Application GB 2 294 591 A, Published, European Patent Application EP 0 553 791 A, IEDM 1998 San Francisco: Y. S. Chun et al. and 1997 Symp. On VLSI Tech. Digest of Tech. Papers: J. M. Drynan et al., pp. 151, 152.
Tantalum oxide (Ta
2
O
5
) capacitors have been known for decades. Their high specific capacitance is substantially based on the relatively high dielectric constant and the low thickness of the tantalum oxide dielectric layer. Furthermore, a surface area which is as large as possible is important for a high specific capacitance, in which case, as is known in particular from electrolytic capacitors, an enlarged-area surface, which has been roughened as much as possible, of the electrode is of importance.
MIM/MIS capacitors have already long been used for dynamic random access memories (DRAMs). Capacitors which have a first electrode made from tungsten, a tantalum pentoxide dielectric and a second electrode made from, for example, titanium nitride (TiN) are known from the reference by Drynan et al., 1997, Symposium on VLSI Technology Digest of Technical Papers, pp. 151 to 152. It is also known (EP 0 553 791), in a capacitor with a silicon semiconductor electrode, to produce a roughened surface of the electrode by anodic etching, selective etching, etching with the additional action of UV light, dry etching of silicon or of an amorphous silicon layer or by recrystallization of an amorphous silicon layer which was previously applied (known as the hemispherical graining (HSG) process).
A DRAM capacitor and its fabrication method are known from U.S. Pat. No. 5,760,434. One capacitor electrode, which is referred to as the bottom electrode and is connected to the transistor of the memory cell, in this document consists of TiN. It is in this case a thin film in the form of a cup on silicon oxide which forms the surrounding side wall. The inner wall of the TiN layer, which is of a cup-like shape, is coated with silicon. The silicon is converted into hemispherical grained silicon with the aid of the HSG process, so that the silicon on the TiN substrate which remains unchanged has the known grained structure/structural surface with a surface area which has been enlarged a number of times. This enlarged surface area of the conductive HSG polysilicon forms the electrode surface with is coated with a dielectric. The dielectric is coated with the second electrode (top electrode) to complete the capacitor.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a miniaturized capacitor with a solid-state dielectric, in particular for integrated semiconductor memories, e.g. DRAMs, and a method for fabricating such a capacitor which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the two electrodes which adjoin the dielectric, in particular the surface of the bottom electrode, consist of an electronically conductive metal with a correspondingly high electrical conductivity, yet nevertheless the electrode surface has a greatly enlarged surface area, as can be achieved with the HSG process for semiconductor materials.
With the foregoing and other objects in view there is provided, in accordance with the invention, a miniaturized capacitor containing a first metal electrode having a predetermined macroscopic form. The first metal electrode has a surface and a region formed of tungsten silicide disposed close to the surface. The first metal electrode has a grown layer containing grained tungsten silicide forming an enlarged surface area disposed on a surface of the region. A solid-state dielectric is disposed on the first metal electrode including the region having the enlarged surface area. A second electrode is disposed on the solid-state dielectric.
The particular features of the present invention can be seen in particular from an advantageous fabrication method according to the invention, which is described below, for the miniaturized solid-state capacitor according to the invention.
For a DRAM capacitor, it is known to provide a form with a macroscopically enlarged surface area for its first (bottom) electrode. By way of example, this may be, as well as the form of a bell or the form of a bore, the form of a column.
Macroscopic forms of this type are sufficiently well known for the relevant capacitors in order to achieve a high capacitance.
In the invention, it is provided that the material of the first electrode, at least in the region below its electrode surface, has an electrical conductivity that is as good as possible. Therefore, according to the invention, either the entire electrode or at least that region of the electrode that is close to the surface is formed of tungsten silicide, which has a good electronic, i.e. metallic, conductivity. For the second case described above, it is alternatively possible, for the invention, to provide polysilicon as the core with a tungsten silicide region which is close to the surface.
According to the invention, the tungsten silicide of the first electrode or at least of its region which is close to the surface contains a stoichiometric excess of silicon. The silicon content may be x=2.0 to 2.5 in the WSi
x
.
A first layer of tungsten silicide which is in this case substoichiometric, for example WSi
1.8
, with a silicon content of between, for example, 1.5 and 1.9, is applied to the surface of this preferably superstoichiometric tungsten silicide. The thickness of a layer of this type is approximately 10 to 30 nm. A layer of this type can be applied, for example, using known chemical vapor deposition (CVD) processes using, for example, tungsten fluoride (WF
6
) and, for example, silane.
A further layer of pure silicon, or silicon without any additives, is applied to the first layer, once again, for example, with the aid of a CVD process. This layer is, for example, 10 to 30 nm thick.
The first (bottom) electrode with these two coatings then undergoes a heat treatment at, for example, 800 to 1100° C. for from, for example, 1 to 10 sec in an inert atmosphere. During the process step, the material of the substoichiometric first layer changes into at least substantially stoichiometric tungsten silicide WSi
2
. The invention exploits the fact that, with the process parameters indicated, this transition to stoichiometric tungsten silicide is accompanied by growth of graining. This is grain growth in or at least on the surface of the first layer. The graining of the first layer that occurs results in a significantly enlarged surface area of the electrode surface of the first electrode that is of relevance for the capacitor.
In the method step of the invention that follows, the silicon of the second layer that is still present is etched away down to the first layer, which now has the graining. Consequently, the tungsten silicide surface is completely exposed. It is now recommended to passivate the grained surface of the first electrode. A thermal nitride coating in substantially a single layer, for example with a thickness of less than 1 nm, is suitable for this purpose. The formation of nitride may take place in particular through the action of NH
3
. The purpose of the passivation is to avoid the formation of any silicon dioxide on the electrode surface. This would in fact considerably reduce the capacitance of the capacitor.
Then, the actual dielectric, for example SiN, of the capacitor according to the invention is applied to the surface of the first electrode which has been fabricated according to the invention and of which the surface area has been enlarged a number of times by the graining achieved. For this application, CVD
Bertagnolli Emmerich
Schlösser Till
Willer Josef
Flynn Nathan J.
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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