MIM capacitor and manufacturing method therefor

Details MIM capacitor and manufacturing method therefor MIM capacitor and manufacturing method therefor

2003-03-10

2004-06-08

Dang, Phuc T. (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S308000

Reexamination Certificate

active

06746912

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a structure of and a manufacturing method for a metal insulator metal (MIM) capacitor in a microwave monolithic integrated circuit utilizing semiconductor technology and, more specifically, compound semiconductor technology.
2. Description of the Related Art
In a monolithic integrated circuit (hereinafter referred to as MMIC), if a bypass capacitor is connected to the outside of a package, noise is caused in a connecting wire between the IC chips and the package, and this small noise causes the deterioration of the IC characteristics. Therefore an MIM capacitor has been used as a bypass capacitor to accommodate power noise.
As an example of a MMIC using such an MIM capacitor, Japanese unexamined patent application publication No.7-21710 discloses an MMIC prepared by depositing on a Ga—As substrate a lower electrode, a silicon oxide layer, a silicon nitride layer, a silicon oxide layer, and an upper electrode in that order.
The MIM capacitor is constructed such that the silicon nitride layer is positioned between silicon oxide layers in order to complement the withstand voltage of the silicon nitride layer. The MIM capacitor however has a problem that the overall dielectric constant becomes lower because silicon oxide has a dielectric constant lower than that of silicon nitride. Also, when the MIM capacitor is prepared on the Ga—As substrate at 400° C. or more, As is liberated and thus the Ga—As substrate deteriorates. Further, when the silicon oxide layers and the silicon nitride layer are deposited at 400° C. by a CVC method, thin and flat silicon oxide layers cannot be formed with half or less than half the thickness of the silicon nitride layer. Hence, a dielectric layer of the MIM capacitor composed of three layers, which are the silicon oxide layer, the silicon nitride layer, and the silicon oxide layer, has twice or more than twice the thickness of a dielectric layer simply composed of silicon nitride layers. Thus, preparing a high-capacity bypass capacitor with an MIM capacitor makes preparing small MMICs difficult because of the large MIM capacitor.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to solve the problems described above by providing a downsized, high-capacity MIM capacitor provided on a compound semiconductor substrate.
To this end, according to one aspect of the present invention, there is provided an MIM capacitor comprising a lower electrode comprising a plurality of metal layers including a top metal layer, an upper electrode, and a dielectric layer positioned between said lower electrode and said upper electrode. The entire surface of the top metal layer is oxidized to form an insulating metal oxide layer.
Pursuant to another aspect of the present invention, there is provided a method of manufacturing an MIM capacitor. The manufacturing method comprises providing a lower electrode comprising a plurality of metal layers, including a top metal layer, and oxidizing the top metal layer of the lower electrode. A dielectric layer is provided on the oxidized top metal layer and an upper layer is provided on the dielectric layer. The dielectric layer may be formed of silicon nitride. The manufacturing method may further comprise oxidizing the dielectric layer. Both oxidizing steps are performed by heating at between 200 and 400° C.
Thus, the metal oxide layer can be formed with a thin thickness without deteriorating the withstand voltage characteristics of the MIM capacitor. As a result, a downsized high-capacity MIM capacitor can be formed, and consequently downsized MMICs can be obtained.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.


REFERENCES:
patent: 6475854 (2002-11-01), Narwankar et al.
patent: 2 337 633 (1999-11-01), None
patent: 3-203261 (1991-09-01), None
patent: 7-161833 (1995-06-01), None
patent: 11-354720 (1999-12-01), None

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