Microprocessor with pipelining, memory size evaluation, micro-op

Details Microprocessor with pipelining, memory size evaluation, micro-op Microprocessor with pipelining, memory size evaluation, micro-op

1996-12-05

1999-04-20

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711117, G06F 1200

Patent

active

058954970

ABSTRACT:
Circuits, systems and methods for operating a processor to process a plurality of sequentially arranged instructions. The method includes various steps, such as receiving (54) into a processor pipeline an instruction from the plurality of sequentially arranged instructions. Next, determines (56) whether the received instruction comprises a memory access instruction. A memory access instruction is operable to access memory information of a specifiable size. In response to determining that the received instruction comprises a memory access instruction, the method generates (58) at least one micro-operation code corresponding to the memory access instruction and it also sets (60) a tag to the at least one micro-operation code, where the set tag requests a subsequent evaluation of the specifiable size. After the tag is set, the method later detects (64, 72) the set tag and, in response to the set tag, retrieves (66, 74) a current value of the specifiable size.

REFERENCES:
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patent: 5155817 (1992-10-01), Kishigami et al.
patent: 5167026 (1992-11-01), Murray et al.
patent: 5542058 (1996-07-01), Brown, III et al.
patent: 5581719 (1996-12-01), Stedy, Jr. et al.
patent: 5630149 (1997-05-01), Bluhm

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