Microprocessor system for simultaneously accessing multiple...

Details Microprocessor system for simultaneously accessing multiple... Microprocessor system for simultaneously accessing multiple...

2008-05-05

2010-12-07

Chan, Eddie P (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

Reexamination Certificate

active

07849299

ABSTRACT:
Provided is a means for accessing multiple entries from a branch history table (BHT) in a single clock cycle, in the context of pipelined instruction processing. In a first clock cycle, a plurality of conditional branch instructions is fetched. A value is accessed from a global history record (GHR) of conditional branch resolutions and predictions for a fetched conditional branch instruction. An associated instruction address is hashed with a left-shifted GHR value. The result is used to access a word in an indexed BHT stored in a single-port random access memory (RAM). The word comprises a branch direction count for the plurality of fetched conditional branch instructions. In a second clock cycle a conditional branch instruction is executed at an execute stage and the BHT is written with an updated branch direction count in response to a resolution of the executed conditional branch instruction.

REFERENCES:
patent: 5758143 (1998-05-01), Levitan
patent: 5805878 (1998-09-01), Rahman et al.
patent: 6347369 (2002-02-01), Witt
patent: 6920549 (2005-07-01), Ukai
patent: 7472263 (2008-12-01), Yokoi

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