Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – Groove
Reexamination Certificate
1999-05-28
2001-09-18
Clark, Sheila V. (Department: 2315)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
Groove
C257S499000
Reexamination Certificate
active
06291875
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to microfabricated devices, and more particularly to three-dimensional devices fabricated with high vertical to horizontal aspect ratios. This invention results in high-aspect-ratio devices that may be fabricated with integrated circuitry on the same substrate using conventional microfabrication techniques.
BACKGROUND OF THE INVENTION
MicroElectroMechanical Systems (MEMS) combine mechanical structures and microelectronic circuits to create integrated devices. MEMS have many useful applications such as microsensors and microactuators. Examples of microsensors include inertial instruments such as accelerometers and gyroscopes, detectors for gasses such as carbon-monoxide, and pressure sensors. Examples of microactuators include optical mirrors used for video displays, switching arrays, and disk-drive head actuators used for increasing track density.
Many MEMS-based devices utilize electrical circuits combined with air-gap capacitors to sense motion, or to apply electrostatic forces to a movable structure. Air-gap capacitors are often formed between sets of capacitor plates anchored to a substrate interleaved with plates attached to a movable structure. The performance of many capacitive-based MEMS improves as: 1) the overlap area of capacitor plates increases, 2) the distance between the stationary and movable capacitor plates decreases, 3) the compliance of the structure varies dramatically in different directions, and 4) the mass of the structure increases. Each of these performance issues is enhanced using high-aspect-ratio semiconductor technologies, wherein thickness or depth of fabricated structures is much larger than small lateral dimensions such as width of flexible beams and gaps between capacitor plates.
Electrical interfaces for capacitive-based MEMS require electrically isolated nodes spanned by one or more variable capacitors such as an air-gap capacitor. Thus, capacitive interfaces using capacitors formed between structural elements require electrical isolation between these structural elements.
The performance of devices such as accelerometers and gyroscopes may benefit from combining high-aspect-ratio structures with circuits integrated in the same substrate. Hence, a high-aspect-ratio structure etched into a single-crystal silicon substrate that also contains integrated circuits is of particular interest. Of even greater interest is a process sequence that yields structures and circuits in the same substrate but does not significantly alter complex and expensive circuit fabrication processes. Such a process sequence enables cost-effective manufacture of devices comprising integrated circuits and structures on a single substrate.
For improved performance, an integrated MEMS process should address three issues. First, the structural elements should be formed by a high-aspect-ratio process. Second, fabrication of mechanical structures should have a minimal impact on fabrication of associated circuitry on the same substrate. Third, structural elements should be electrically isolated from one another, the substrate, and circuit elements except where interconnection is desired.
SUMMARY OF THE INVENTION
In one aspect, the invention is directed to a microfabricated device. The device includes a substrate that is etched to define mechanical structures that are anchored laterally to the remainder of the substrate. Electrical isolation where mechanical structures are attached to the substrate is provided by trenches etched in the substrate that are subsequently lined with an insulating material.
Circuit elements may be formed in the substrate material. Conducting material deposited over isolating trenches may be used to interconnect electrically isolated circuit and structural elements. The insulating lining deposited in the trenches may fill the trenches or the lining may be filled with a second material that is not necessarily insulating. The substrate may also include a device layer in which one or more structures and electrical circuits are formed, a handle layer, and a sacrificial layer between the device and handle layers. A portion of the sacrificial layer may be removed to free the structures from the substrate. The sacrificial layer may include silicon dioxide, the substrate or device layer may include single-crystal or epitaxial silicon, the isolation material may include a silicon nitride, and the trench fill material may include polycrystalline silicon.
Performance of devices fabricated in accordance with the invention is improved due to the proximity of interface circuitry built into the same substrate as the microstructures. Performance of microstructures is improved due to the high-aspect-ratio fabrication that yields larger mass, air-gap capacitors with larger sensitivity, and improved suppression of undesired deflections-particularly deflections out of the plane of the substrate. The invention is compatible with existing microfabrication techniques and is compatible with established integrated circuit fabrication processes.
REFERENCES:
patent: 5084408 (1992-01-01), Baba et al.
patent: 5198390 (1993-03-01), MacDonald et al.
patent: 5326726 (1994-07-01), Tsang et al.
patent: 5343064 (1994-08-01), Spangler et al.
patent: 5445988 (1995-08-01), Schwalke et al.
patent: 5447067 (1995-09-01), Biebl et al.
patent: 5495761 (1996-03-01), Diem et al.
patent: 5504026 (1996-04-01), Kung
patent: 5506175 (1996-04-01), Zhang et al.
patent: 5569852 (1996-10-01), Marek et al.
patent: 5574222 (1996-11-01), Offenberg
patent: 5576250 (1996-11-01), Diem et al.
patent: 5578755 (1996-11-01), Offenberg
patent: 5592015 (1997-01-01), Iida et al.
patent: 5616523 (1997-04-01), Benz et al.
patent: 5627317 (1997-05-01), Offenberg et al.
patent: 5627318 (1997-05-01), Fujii et al.
patent: 5631422 (1997-05-01), Sulzberger et al.
patent: 5719073 (1998-02-01), Shaw et al.
patent: 5723353 (1998-03-01), Muenzel et al.
patent: 5747353 (1998-05-01), Bashir et al.
patent: 5747867 (1998-05-01), Oppermann
patent: 5756901 (1998-05-01), Kurle et al.
patent: 5798283 (1998-08-01), Montague et al.
patent: 5847280 (1998-12-01), Sherman et al.
patent: 5847454 (1998-12-01), Shaw et al.
patent: 5882532 (1999-03-01), Field et al.
patent: 5959208 (1999-09-01), Muenzel et al.
patent: 6067858 (2000-05-01), Clark et al.
patent: 6180536 (2001-06-01), Chong et al.
patent: 6199874 (2001-03-01), Galvin et al.
U.S. application No. 08/874,568, Brosnihan et al., filed Jun. 13, 1997.
Brosnihan, T. et al., “Enbedded Interconnect and Electrical Isolation for High-Aspect-Ratio, SOI Inertial Instruments”,Proc. 1997 International Conference on Solid-State Sensors and Actuators,Chicago, IL, pp. 637-640, Jun. 16-19, 1997.
Sridhar, U. et al., “Isolation Process for Surface Micromachined Sensors and Actuators, ”iMEMS '97 International MEMS Workshop, National University of Singapore, Singapore, Dec., 1997.
Keller, Christopher, Microfabricated Silicon High Aspect Ratio Flexures for In-Plane Motion, Doctoral Dissertation University of California, 1998.
Clark William A.
Juneau Thor N.
Lemkin Mark A.
Roessig Allen W.
Analog Devices IMI, Inc.
Clark Sheila V.
Vierra Magen Marcus Harmon & DeNiro LLP
LandOfFree
Microfabricated structures with electrical isolation and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Microfabricated structures with electrical isolation and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Microfabricated structures with electrical isolation and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2538667