Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-10-29
1999-11-23
Auve, Glenn A.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
326 16, 714724, G01R 3128
Patent
active
059919108
ABSTRACT:
A free-running microcontroller (i.e., one without any reset signal) is shown with special mode enable detect logic for placing the microcontroller into the test or special operations mode, without the benefit of a dedicated pin for such purposes. Rather, the instant invention implements the methodology of first applying a test voltage to indicate to the free-running microcontroller that the test mode is to be entered. Since the device has no reset signal to interrupt normal operation once it has begun, the test voltage is applied before the power supply V.sub.DD to ensure that the device enters test mode before it can enter normal operation.
REFERENCES:
patent: 4733168 (1988-03-01), Blankenship et al.
patent: 5786703 (1998-07-01), Piirainen
Ellison Scott
Hofhine Paul
Hull Richard L.
Auve Glenn A.
Chichester Ronald L.
Katz Paul N.
Microchip Technology Incorporated
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