Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-01-22
2000-06-13
Hafiz, Tariq R.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714 38, G06F 9445
Patent
active
060759410
ABSTRACT:
A microcomputer contains an electrically erasable flash memory for storing a program under development and a debugging circuit 7 having a dedicated input/output terminal for connection to an external ICE 14, and the debugging circuit 7 has a function of communication with a CPU 1, a function of communication with the ICE 14, a function of tracing the operating condition of the CPU 1, a break function of generating a debug interrupt, a function of writing a program code from the ICE 14 into the flash memory 6 and a function of sending the contents of the flash memory 6 to the ICE 14.
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Akatsuki Tadayuki
Itoh Sakae
Kanzaki Teruaki
Nakamura Yasuhiro
Numata Tsutomu
Chavis John Q.
Hafiz Tariq R.
International Business Machines - Corporation
Mitsubishi Denki & Kabushiki Kaisha
Mitsubishi Electric System LSI Design Corporation
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