Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2001-10-01
2002-08-06
Talbott, David L. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S685000, C257S686000, C257S723000, C257S777000
Reexamination Certificate
active
06429511
ABSTRACT:
TECHNICAL FIELD
The present invention relates to wafer-level packaging techniques, and more specifically to wafer-level, chip-scale packaging of semiconductors.
BACKGROUND ART
Currently, there are a number of wafer-to-wafer bonding techniques that have been used for packaging semiconductor devices. Techniques used have included silicon-to-glass anodic bonding, silicon-to-silicon fusion bonding, and wafer-to-wafer bonding using intermediate materials as the actual bonding media. Such intermediate materials have included silicon dioxide, and soft metals such as gold, indium, and aluminum, and have been bonded using electrical, thermal and/or compression techniques.
There are various problems with all of these techniques. The anodic bonding of a glass wafer to a silicon wafer involves the use of high voltages that can be detrimental to the electronic circuits present on the silicon wafer. Similarly, the silicon-to-silicon bonding has to be done at very high voltage and also at a high temperature. Both of these techniques can melt metals with lower melting points than the temperature required to perform the bonding so they cannot be used with certain types of semiconductor devices on silicon wafers. Materials such as glass frit involve relatively large bonding areas which results in an increased die size thereby limiting the number of devices that can be fabricated on a given wafer. Further, some of these techniques cannot assure reliable hermetic seals of the packaged device.
One example of such packaging method is shown in U.S. Pat. No. 5,448,014 to Kong et al. However, Kong et al. requires multi-layer standoffs to adjust the distance between the two wafers. Additionally, the disclosed use of different materials for each of the wafers can cause potentially adverse consequences due to the different thermal coefficients of expansion of the materials when the package is manufactured using heat as disclosed.
A relatively simple process that would provide a non-electrical, low temperature method for hermetically packaging micro devices on or in semiconductor wafers has long been sought. Further, a process has been sought which uses processes that are standard, or close to standard, and presently used in a typical semiconductor laboratory or manufacturing facility.
Also, in the past, making electrical contact to the packaged devices was difficult because existing methods did not provide a wafer-to-wafer seal that allows the electrical conductor to pass through the wafer package itself without the use of epoxy, grommets, or sealing rings in the through holes around the wires. The previous sealing techniques, besides being very small and difficult to implement, were subject to leaking because of the flexing of the wire in the seal, which would open the seal.
DISCLOSURE OF THE INVENTION
The present invention provides a microcap wafer-level package in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer has gaskets formed thereon. Bonding pad gaskets match the perimeters of the bonding pads, and a peripheral pad gasket matches the peripheral pad on the base wafer. Wells are located inside the perimeters of the bond pad gaskets and are formed to a predetermined depth in the cap wafer. The cap wafer is then placed over the base wafer so as to bond the gaskets to the pads and form a hermetically sealed volume between the bonding pad gaskets and the peripheral pad gasket. The cap wafer is thinned to form a “microcap”. Essentially, the microcap is thinned below the predetermined depth until the wells become through holes that provide access to the bonding pads inside the package, but outside the hermetically sealed volume, for conductors from a micro device utilizing system. This arrangement assures a highly reliable hermetic seal for the wafer-level package, which allows electrical connections without passing through a seal. Further, this process permits the wafers to be made thinner than previously practical because it forms the microcap in situ and avoids the handling of the fragile microcap during assembly.
The present invention further provides a microcap wafer-level package in which a micro device is connected to bonding pads on a base wafer. A peripheral pad on the base wafer encompasses the bonding pads and the micro device. A cap wafer is processed to form wells of a predetermined depth in the cap wafer. A conductive material is coated onto the walls of the wells in the cap wafer. The cap wafer has contact gaskets and a peripheral gasket formed thereon where the contact gaskets are capable of being aligned with the bonding pads on the base wafer, and the gasket matches the peripheral pad on the base wafer. The cap wafer is then placed over the base wafer so as to bond the contact gaskets and gasket to the pads and form a hermetically sealed volume within the peripheral gasket. The cap wafer is thinned below the predetermined depth until the conductive material is exposed to form conductive vias through the cap wafer to outside the hermetically sealed volume. This via arrangement assures a reliable, high conductivity, hermetically sealed connection into the wafer-level package. Further, this process permits the wafers to be made thinner than previously practical because it forms the microcap in situ and avoids the handling of the fragile microcap during assembly.
The present invention provides an electrical or mechanical device in a wafer-level, chip-scale package that hermetically seals the semiconductor device while providing electrical or thermal connection through one of the wafers.
The present invention further provides a device in a wafer-level, chip-scale package that allows an electrical connection to the device to be made through the wafer sealing the package itself.
The present invention further provides a device in a wafer-level, chip-scale package that allows an electrical connection to the device to be made through openings in a cap wafer to bonding pads, which are individually sealed at the same time the device, is sealed.
The present invention further provides a wafer-level, chip-scale packaging technique utilizing a low-temperature, batch process done at the wafer level which results in a hermetic seal and allows electrical contacts to be made to standard bonding pads on a base wafer.
The present invention further provides a relatively simple process that results in a hermetic seal for semiconductor devices which does not require high voltages or temperatures.
The present invention further provides a method of manufacturing a wafer package utilizing process steps and equipment that are standard or close to standard to the processes and equipment used in a typical semiconductor laboratory or manufacturing facility.
The above and additional advantages of the present invention will become apparent to those skilled in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.
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patent: 3784883 (1974-01-01), Duncan et al.
patent: 5373627 (1994-12-01), Grebe
patent: 5448014 (1995-09-01), Kong et al.
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patent: 0828346 (1998-03-01), None
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Bell Tracy E.
Desai Yogesh M.
Geefay Frank S.
Ruby Richard C.
Agilent Technologie,s Inc.
Cruz Lourdes
Talbott David L.
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