Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Reexamination Certificate
2000-03-31
2004-03-30
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
C712S247000, C712S235000
Reexamination Certificate
active
06715065
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention is directed to an information processing apparatus incorporating micro program control method, more specifically to a micro program control method and apparatus thereof for data processing with microprogram control, which allows high speed fetching of micro instructions from control storage without increasing the program capacity of microprograms.
A first example of the Prior Art technology performs micro program control, which has a field for specifying the branch target address of next clock cycle (referred to as a cycle, hereinbelow) by a micro instruction and a field for controlling a processor.
Now referring to
FIGS. 5 through 8
an embodiment in accordance with the first example of the Prior Art technology and the execution procedure will be described.
Referring at first to
FIG. 6
, there is shown a format of micro instruction in accordance with first example of the Prior Art technology, which instruction comprises a page address field
600
of branch target of the micro instruction, an end judgment field
601
for determining whether or not the micro program terminates in next cycle, a branch condition field
602
for use in the branch judgment, and a control field
603
for controlling the execution in next cycle. In first example of the Prior Art technology, a pair of micro instructions composes a page.
FIG. 5
is a block diagram of a micro program controller embodied by the first example of the Prior Art technology. This controller comprises an instruction fetch unit
50
, a read/branch unit
51
for reading and branching micro instructions, and an execution unit
52
for executing computations such as additions and data shifts. The execution unit
52
includes ALUs, decoders and registers.
The an instruction fetch unit
50
comprises a start address register
510
for storing the start address of a micro program. The read/branch unit
51
is constituted of an end judgment circuit
531
for generating a termination signal of micro program by referring to the end judgment field
601
of the micro instruction, an address selector
520
for determining whether to start, continue, or terminate a micro program by referring to the termination signal of the micro program, an address register
511
for storing the page address of micro instruction, a control storage
530
for storing micro instructions, a branch judgment circuit
532
for determining whether to branch or not by referring to both the micro instruction read out during the immediately preceding cycle and the result of execution of the previous cycle, a bank selector
521
to which one instruction selected from two micro instructions read out in accordance with the branch judgment signal is output, and a data register
512
for storing the branch condition field
602
of micro instruction and the control field
603
. The control storage
530
has two banks, namely bank
0
and bank
1
, specified by the same address, and stores a micro instruction page. As have been described above one page is of the size of two micro instructions.
Next referring to the timing chart shown in FIG.
7
and to the flow chart shown in
FIG. 8
, the execution procedure of a micro program control embodied by the first example of Prior Art technology.
In cycle (C-
1
), a start address A
10
of a micro program stored in the start address register
510
in the instruction fetch unit
50
is transferred to the read/branch unit
51
. The start address A
10
is input to the address selector
520
and stored in the address register
511
after the transfer.
In cycle (C
0
), the page address of the control storage
530
is specified by the start address A
10
of the micro program stored in the address register
511
, to read out a micro instruction M
100
from the bank
0
and another micro instruction M
101
from the bank
1
. The bank selector
521
selects either of two micro instructions M
100
and M
101
read out from the banks to start a branch operation B
10
. In the flow chart (FIG.
8
), the micro instruction M
100
read out from the bank
0
is selected at the branch operation B
10
. The page address field A
20
of the selected micro instruction M
100
is input to the address selector
520
and stored in the address register
511
, while the branch condition field (not shown) and control field i
100
in the micro instruction M
100
selected by the bank selector
521
are stored in the data register
512
.
In cycle (C
1
), as similar to the preceding cycle (C
0
), the page address A
20
of the control storage
530
is selected for reading out and branching the micro instructions M
200
and M
201
. The control field i
100
of the micro instruction M
100
stored in the data register
512
is transferred to the execution unit
52
to start executing operations. In the procedure shown in this flow chart (FIG.
8
), for the sake of facilitating the understanding of the illustrated procedure, the branching selects alternately bank
0
and bank
1
. As the result of foregoing execution, the micro instruction controls the execution unit in the following order: i
100
(cycle C
1
), i
201
(cycle C
2
), i
310
(cycle C
3
), i
421
(cycle C
4
).
In a second example of the Prior Art technology a micro instruction having one field of branched target address following Nth cycle (where N≧2) and another field for controlling the execution following Nth cycle (where N≧2) controls the micro program. This technology has been devised for accelerating said first technology, as disclosed in the U.S. Pat. No. 4,494,195.
Now referring to
FIGS. 9 through 12
an embodiment in accordance with the second Prior Art technology (in case of N=2) and the execution procedure thereof will be described below.
FIG. 10
shows an exemplary format of a micro instruction in accordance with the second Prior Art technology, with N=2, which contains a field of page address following the next cycle
1000
, a field of end judgment following the next cycle
1001
for use in determining whether the micro program terminates by second cycles, a field of branch condition following the next cycle
1002
for use in the branch judgment by the cycle following the next, and a field of control following the next cycle
1003
for use in controlling the execution in the cycle following the next. In this second Prior Art technology a set of four micro instructions composes a page.
FIG. 9
shows a block diagram of a micro program controller embodied by the second Prior Art technology, with N=2. This controller unit, as similar to preceding first technology, comprises an instruction fetch unit
90
, a read/branch unit
91
, and an execution unit
92
.
In second technology of the Prior Art, where N=2, in order to obtain the same micro program control as first technology, a start address should be fetched at the beginning of the micro program, in addition to two micro instructions to be executed in the cycle following the next (for bank
0
and bank
1
, respectively). The instruction fetch unit
90
thus comprises a start address register of micro program
910
, a second cycle micro instruction register (bank
0
)
911
for use in storing second cycle micro instruction (bank
0
), and another second cycle micro instruction register (bank
1
)
912
for use in storing second cycle micro instruction (bank
1
).
The read/branch unit
91
comprises a bank selector
920
for selecting either one of second cycle micro instruction register
911
(for bank
0
) or second cycle micro instruction register
912
(for bank
1
), an end judgment circuit
931
, an address selector
921
, an address register
913
, a control storage
930
including
4
banks constituted of bank
00
, bank
01
, bank
10
, and bank
11
, a branch judgment circuit
932
, a bank selector
922
for selecting either one of micro instruction read from bank
00
and bank
10
of the control storage
930
, another bank selector
923
for selecting either one of micro instruction read from bank
01
and bank
11
of the control storage
930
, anothe
Ebata Atsushi
Kato Takeshi
Yamamoto Michitaka
A. Marquez, Esq. Juan Carlos
Chan Eddie
Fisher Esq. Stanley P.
Hitachi , Ltd.
Li Aimee J.
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