Methods to reduce stress on a metal interconnect

Details Methods to reduce stress on a metal interconnect Methods to reduce stress on a metal interconnect

2005-09-27

2005-09-27

Thompson, Craig A. (Department: 2813)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Multiple layers

C438S660000, C438S688000, C438S761000

Reexamination Certificate

active

06949475

ABSTRACT:
Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.

REFERENCES:
patent: 4499653 (1985-02-01), Kub et al.
patent: 6709989 (2004-03-01), Ramdani et al.

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