Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1997-12-12
2001-04-10
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
06216246
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to methods to make a dynamic random access memory (DRAM) fully compatible with a static random access memory (SRAM).
DRAM and SRAM are two major types of memory devices in the Integrated Circuit (IC) industry. DRAM of current art always has lower performance relative to SRAM, while SRAM is more expensive. Therefore, DRAM of current art is used for cost-sensitive applications, while SRAM is used for applications that require performance, power efficiency, or user-friendliness. Since the logic circuits of current art is operating at much high frequencies than DRAM, memory access operations are often the performance bottleneck for computers. A typical solution for this performance bottleneck is to use a large number of low cost DRAM's as the main memory, while using a smaller number of high performance SRAM's as cache memory. This multiple level memory structure provides necessary compromises to balance cost efficiency and performance requirements. However, complex logic circuits are needed to assure data consistency of this memory structure. In many cases, memory operations are still the performance bottleneck for computer systems. It is therefore highly desirable to be able to manufacture high performance and cost efficient memories to remove multiple level memory structures in computer systems.
The need to manufacture different types of memory devices causes tremendous wastes in the IC industry. DRAM's are typically manufactured by 4 layer poly, double layer metal (4P2M) technology; SRAM's are typically manufactured by 2 layer poly, double layer metal (2P2M) technology; logic circuits require technologies with many metal layers such as a single layer poly, 4 layer metal (1P4M) technology. Details of transistor manufacture procedures are also different between memory and logic. DRAM technologies emphasize on leakage current reduction and high voltage tolerance, so it needs to use thick gate, long channel transistors with higher threshold voltage. Logic circuits emphasize on performance, so they prefer thin gate, short channel transistors with lower threshold voltage. An SRAM technology needs to have special modules to build poly resistors. Due to these conflicting requirements, researchers in the IC industry must develop different manufacturing technologies to build DRAM's, SRAM's, and logic circuits separately. It is therefore highly desirable to simplify those conflicting needs from different types of products.
One approach to solve the above long-existing problem is to improve the data access rate of DRAM using parallel processing and pipeline concepts in DRAM design. Well-known products using such approaches are the synchronized DRAM (SDRAM), the RAMBUS system approach, and the multiple-bank DRAM (MDRAM). The major problem for those products is that they are not compatible with existing products. The computer industry does not want to change existing designs to adapt for those new memory structures. The other problem is that these approaches improve data access rate without improving memory latency.
Another approach is to make a DRAM device behaves as an SRAM device using self-refresh circuits. This type of memory device is user-friendly because it has the same interface as conventional SRAM devices. However, they are not very useful because performance of such self-refresh DRAM is as low as conventional DRAM, while it requires high standby power to support self-refresh operations.
The above inventions and developments provided partial solutions to memory design problems, but the computer industry resists to adapt to such partial solutions. Meeting requirements in performance and cost efficiency is not enough. To be successful, a novel solution must be compatible to existing memory devices in every details. U.S. patent application Ser. No. 8,653,620 described methods to make a DRAM as fast as SRAM including a self-refresh mechanism which is completely invisible to external users. U.S. pat. appl. Ser. No. 08/805,290, now U.S. Pat. No. 5,825,704, described methods to build smaller memory device using the same manufacture technologies used to build logic IC products. The above two inventions allow us to make memories faster than SRAM of current art while using silicon area as small as that of DRAM of current art However, there are further detailed problems we must solve to make our products truly compatible with existing industry standards. The present invention is developed to cover those remaining details.
The first issue is the standby power problem. An SRAM consumes almost no power when it is not used. A DRAM consumes power even when the user is not using the memory. There are two major sources for this waste in energy. The most well-known source comes from the memory refresh operations. The self-refresh mechanism described in U.S. pat. appl. Ser. No. 08/653,620, now U.S. Pat. No. 5,748,547, improved energy efficiency for memory refresh, and solved the problem effectively. The other major source comes from the DRAM pre-charge circuits. Bit lines of DRAM are usually pre-charged to a voltage near half of its power supply voltage. In order to make the product fully compatible with SRAM, we must have an internal reference voltage generator to maintain this pre-charge voltage. Reference voltage generators of current art consume standby powers. Because our product is much faster than conventional DRAM, the reference voltage generator need to have much stronger driving capability than those used by conventional DRAM's. It is therefore even more difficult to meet the requirements on standby power. This problem must be solved because the computer industry expects low standby power from SRAM's.
Another important issue is a reliability problem known as “alpha particle problem”—high energy particles hit an integrated circuit, and change the contents of its memory elements. The memory cells used in our previous inventions are more sensitive to the alpha particle problem than conventional SRAM devices. It is therefore desirable to develop an error correction mechanism to correct errors caused by the alpha particle problem.
SUMMARY OF THE INVENTION
The primary objective of this invention is, therefore, to provide practical methods to make a DRAM fully compatible with existing SRAM products. This and other objects are accomplished by design and manufacture methods according to the invention, which includes a method to reduce standby power of reference voltage generators and a method to avoid the alpha particle problem using a novel error correction code (ECC) mechanism.
The reference voltage generator of the present invention can adjust the values of output voltage and driving power separately following simple procedures. It has very strong driving power to maintain the reference voltage, which is necessary to support high speed operation of memory devices of the present invention. In the mean time, its standby power can be reduced by orders of magnitudes using simple control mechanism, which is necessary to make our memory device compatible with the properties of existing SRAM products. There is no need to use feedback circuits or operation amplifiers, so the circuit is extremely stable and reliable. It is an ideal reference voltage generator to generate the bit line pre-charge voltage for a DRAM designed to emulate an SRAM device. The unique features of the ECC protection of the present invention avoid RC delay problems in prior art ECC circuits, which is necessary to support high speed operation of our products. The alpha particle problem is no longer an issue. All the supporting circuits can use repeated layouts, which is very important for memory design. The manufacture technology for embedded IC is simplified dramatically, which allow us to have high performance logic circuits. The memory devices of the present invention is therefore compatible in every detailed feature with existing SRAM products.
While the novel features of the invention are set forth with particularly in the appende
Cady Albert De
Lin Bo-In
Ton David
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