Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-08-24
2003-03-04
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S782000, C438S791000, C118S728000
Reexamination Certificate
active
06528364
ABSTRACT:
TECHNICAL FIELD
This invention relates to methods to form electronic devices, for example capacitors, antifuses, transistor gate and other constructions, and to methods to form a material over a semiconductive substrate.
BACKGROUND OF THE INVENTION
As the density of DRAM cells increases, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature sizes continue to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell design and structure become important. The feature size of higher density DRAMS, for example 256 Mb, will be on the order of 0.25 micron and less. Such overall reduction in cell size drives the thickness of the capacitor dielectric layer to smaller values, and conventional capacitor dielectric materials such as SiO
2
and Si
3
N
4
might become unsuitable. However it would be desirable to utilize silicon oxides and nitrides in spite of the reduced thicknesses due to the ease of use and available thorough understanding to integrate these materials in DRAM process flows. Yet processing associated with chemical vapor deposition of thin silicon nitride films in certain environments has also created other problems not directly associated with the capacitors.
For example, one prior art technique is the fabrication of stacked capacitors in a container shape within a borophosphosilicate glass layer (BPSG) to form the storage capacitors in DRAM circuitry. Here, a container opening is formed in a planarized layer of BPSG over a desired node location, typically in the form of a conductive polysilicon plug. The conductive electrode material is deposited to less than completely fill the opening, and then is typically chemical-mechanically polished back to provide a storage node electrode inside of the BPSG opening in the shape of a cup or container. Capacitor dielectric material is then provided over the storage node container, followed by deposition of a conductive cell plate layer which is subsequently patterned.
As circuitry integration and density increases, the corresponding dimensions and thicknesses of the various components also decreases. A typical capacitor dielectric layer in the above construction comprises a silicon dioxide/silicon nitride/silicon dioxide composite (ONO). The first oxide layer formed over the storage node electrode is typically native oxide formed by exposure of the exposed storage node material to ambient air. Silicon nitride is next chemical vapor deposited, for example utilizing a silicon hydride such as dichlorosilane and ammonia. Typical deposition conditions are at sub-Torr pressures and temperatures at or above 680° C., more typically above 700° C. The deposition process and the very thin nature of the typically deposited silicon nitride layer results in pin holes or other defects in the deposited layer. This is typically cured by a dense re-oxidation process which forms the outer silicon dioxide layer of the ONO construction. The prior art re-oxidation conditions for forming this outer oxide layer are conducted wet or dry at a temperature of from 800° C. to 950° C. at atmospheric pressure for from 5 to 30 minutes. Subsequently, a conductive cell plate layer is deposited and patterned over the ONO dielectric layer(s).
However as the nitride thickness of the ONO construction over the storage node electrode fell to below 80 Angstroms, it was discovered that the underlying bulk silicon substrate was oxidizing to the point of circuit destruction. BPSG is known to be extremely diffusive to oxidizing components during the above-described re-oxidation conditions. Silicon nitride, on the other hand, is known to form a good barrier layer to diffusion of such oxidizing gases under such conditions. Yet, the silicon nitride deposited over the BPSG in conjunction with the capacitor dielectric layer formation was apparently inadequate in shielding oxidation of substrate material underlying the BPSG when the deposited silicon nitride layer thickness for the capacitors fell below 80 Angstroms.
The invention was principally motivated with respect to overcoming this problem to enable silicon nitride to continue to be utilized as a capacitor dielectric layer where its thickness fell to below 80 Angstroms in deposition also occurring over a doped oxide layer, such as BPSG.
SUMMARY OF THE INVENTION
The invention comprises forming electronic devices, such as capacitors, antifuses, transistor gate and other constructions, and to methods of forming a material over a semiconductive substrate. In but one implementation, a first electrode and a doped oxide layer laterally proximate thereof are provided over a substrate. A silicon nitride layer is formed over both the doped oxide layer and the first electrode to a thickness of no greater than 80 Angstroms over at least the first electrode by low pressure chemical vapor deposition using feed gases comprising a silicon hydride, H
2
and ammonia. The substrate with silicon nitride layer is exposed to oxidizing conditions comprising at least 700° C. to form a silicon dioxide layer over the silicon nitride layer, with the thickness of silicon nitride over the doped oxide layer being sufficient to shield oxidizable substrate material beneath the doped oxide layer from oxidizing during the exposing. A second electrode is formed over the silicon dioxide layer and the first electrode.
In one implementation, the chemical vapor depositing comprises feed gases of a silicon hydride and ammonia, with the depositing comprising increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. and starting feed of the silicon hydride into the reactor at a temperature less than or equal to 600° C. In one implementation the depositing comprises increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. using a temperature ramp rate of at least 10° C./minute from at least 500° C. to at least 600° C. In preferred implementations, the substrate is rotating during deposition, with the depositing comprising increasing internal reactor temperature from below 500° C. to a maximum deposition temperature above 600° C. and starting the substrate to rotate prior to reaching the maximum deposition temperature. In one implementation, rotation rate of the substrate is reduced upon substantially ceasing flow of at least one reactant gas to the reactor. In one implementation, rotation rate of the substrate is reduced within 1 minute of substantially ceasing flow of the at least one reactant gas to the reactor.
In one implementation, an inert cooling gas is flowed through a chemical vapor deposition reactor to cool a substrate and deposited material after the deposition.
In one implementation, a doped oxide layer is provided over a substrate. The doped oxide layer is chemical-mechanical polished. After the chemical-mechanical polishing, the doped oxide layer is caused to flow in a process comprising at least two steps. A prior in time of the steps comprises an inert atmosphere at a temperature of at least about 700° C. A later in time of the steps comprises an ammonia comprising atmosphere at a temperature of at least about 700° C. and forms a silicon nitride layer over the doped oxide layer.
Other aspects and implementations are described below.
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Niebling John F.
Pompey Ron E.
Wells St. John P.S.
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