Methods, systems and media for managing functional...

Details Methods, systems and media for managing functional... Methods, systems and media for managing functional...

2007-06-26

2007-06-26

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11053220

ABSTRACT:
Methods, systems, and media for managing functional verification of a parameterizable design are disclosed. Embodiments include a system having a testbench configuration module adapted to configure a testbench, the testbench having testbench signals and one or more instantiated components having a plurality of ports of a generic design, where the testbench signals are wired to the plurality of ports. The testbench may also have one or more instantiated special components based on chip-specific versions of the design where the special components are wired to the same ports as the generic design. The system may also include a functional verification manager that, through a component module, observes values in the testbench and automatically configure a verification environment based on the observed values, including automatic insertion of checkers at different levels of hierarchy. The testbench may be a VHDL or Verilog testbench in some embodiments.

REFERENCES:
patent: 6182258 (2001-01-01), Hollander
patent: 6490711 (2002-12-01), Buckley, Jr.
patent: 6530054 (2003-03-01), Hollander
patent: 6581191 (2003-06-01), Schubert et al.
patent: 6591403 (2003-07-01), Bass et al.
patent: 7165231 (2007-01-01), Buckley, Jr.

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